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P1020: dts: Added PCIe DT nodes

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P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-08-27 11:04:04 +00:00 committed by Prabhakar Kushwaha
parent ba827365f7
commit 594708dd9d
4 changed files with 56 additions and 0 deletions
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20
arch/powerpc/dts/p1020-post.dtsi
View File

@ -25,3 +25,23 @@
last-interrupt-source = <255>;
};
};
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* PCIe controller base address 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

12
arch/powerpc/dts/p1020rdb-pc.dts
View File

@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"

12
arch/powerpc/dts/p1020rdb-pc_36b.dts
View File

@ -18,6 +18,18 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"

12
arch/powerpc/dts/p1020rdb-pd.dts
View File

@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"