ddr: altera: Compile ALTERA SDRAM in SPL only
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
parent
86f578ee85
commit
5918afda9d
2
Makefile
2
Makefile
@ -713,7 +713,7 @@ libs-y += drivers/spi/
|
||||
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
|
||||
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
|
||||
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
|
||||
libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
|
||||
libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
|
||||
libs-y += drivers/serial/
|
||||
libs-y += drivers/usb/dwc3/
|
||||
libs-y += drivers/usb/common/
|
||||
|
@ -26,7 +26,7 @@ config TARGET_SOCFPGA_ARRIA5
|
||||
|
||||
config TARGET_SOCFPGA_ARRIA10
|
||||
bool
|
||||
select ALTERA_SDRAM
|
||||
select SPL_ALTERA_SDRAM
|
||||
select SPL_BOARD_INIT if SPL
|
||||
select CLK
|
||||
select SPL_CLK if SPL
|
||||
@ -47,7 +47,7 @@ config TARGET_SOCFPGA_CYCLONE5
|
||||
|
||||
config TARGET_SOCFPGA_GEN5
|
||||
bool
|
||||
select ALTERA_SDRAM
|
||||
select SPL_ALTERA_SDRAM
|
||||
imply FPGA_SOCFPGA
|
||||
imply SPL_STACK_R
|
||||
imply SPL_SYS_MALLOC_SIMPLE
|
||||
|
@ -34,7 +34,7 @@ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
|
||||
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
|
||||
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
|
||||
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
|
||||
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
|
||||
obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
|
||||
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
|
||||
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
|
||||
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
|
||||
|
@ -1,5 +1,6 @@
|
||||
config ALTERA_SDRAM
|
||||
bool "SoCFPGA DDR SDRAM driver"
|
||||
config SPL_ALTERA_SDRAM
|
||||
bool "SoCFPGA DDR SDRAM driver in SPL"
|
||||
depends on SPL
|
||||
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
|
||||
select RAM if TARGET_SOCFPGA_GEN5
|
||||
select SPL_RAM if TARGET_SOCFPGA_GEN5
|
||||
|
@ -6,7 +6,7 @@
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
# Copyright (C) 2014 Altera Corporation <www.altera.com>
|
||||
|
||||
ifdef CONFIG_ALTERA_SDRAM
|
||||
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
|
||||
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
|
||||
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
|
||||
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
|
||||
|
@ -132,7 +132,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
|
||||
/*
|
||||
* SDRAM controller
|
||||
*/
|
||||
#define CONFIG_ALTERA_SDRAM
|
||||
#define CONFIG_SPL_ALTERA_SDRAM
|
||||
|
||||
/*
|
||||
* Serial / UART configurations
|
||||
|
@ -1824,6 +1824,7 @@ CONFIG_SPLASH_SCREEN_ALIGN
|
||||
CONFIG_SPLASH_SOURCE
|
||||
CONFIG_SPLL_FREQ
|
||||
CONFIG_SPL_
|
||||
CONFIG_SPL_ALTERA_SDRAM
|
||||
CONFIG_SPL_ATMEL_SIZE
|
||||
CONFIG_SPL_BOARD_LOAD_IMAGE
|
||||
CONFIG_SPL_BOOTROM_SAVE
|
||||
|
Loading…
Reference in New Issue
Block a user