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ARM: Introduce erratum workaround for 430973

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430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Nishanth Menon 2015-03-09 17:12:01 -05:00 committed by Tom Rini
parent b45c48a7c3
commit 5902f4ce0f
2 changed files with 14 additions and 0 deletions
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1
README
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@ -693,6 +693,7 @@ The following options need to be configured:
NOTE: The following can be machine specific errata. These NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine do have ability to provide rudimentary version and machine
specific checks, but expect no product checks. specific checks, but expect no product checks.
CONFIG_ARM_ERRATA_430973
CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_798870 CONFIG_ARM_ERRATA_798870

13
arch/arm/cpu/armv7/start.S
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@ -200,6 +200,19 @@ skip_errata_798870:
pop {r1-r5} @ Restore the cpu info - fall through pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_454179: skip_errata_454179:
#endif
#ifdef CONFIG_ARM_ERRATA_430973
cmp r2, #0x21 @ Only on < r2p1
bge skip_errata_430973
mrc p15, 0, r0, c1, c0, 1 @ Read ACR
orr r0, r0, #(0x1 << 6) @ Set IBE bit
push {r1-r5} @ Save the cpu info registers
bl v7_arch_cp15_set_acr
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_430973:
#endif #endif
mov pc, r5 @ back to my caller mov pc, r5 @ back to my caller