keystone: set default pci mode to root complex
pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
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@ -15,6 +15,16 @@
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#include <asm/arch/hardware.h>
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#include <asm/arch/psc_defs.h>
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#define MAX_PCI_PORTS 2
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enum pci_mode {
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ENDPOINT,
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LEGACY_ENDPOINT,
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ROOTCOMPLEX,
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};
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#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
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#define DEVCFG_MODE_SHIFT 1
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void chip_configuration_unlock(void)
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{
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__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
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@ -68,6 +78,24 @@ void osr_init(void)
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}
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#endif
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/* Function to set up PCIe mode */
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static void config_pcie_mode(int pcie_port, enum pci_mode mode)
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{
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u32 val = __raw_readl(KS2_DEVCFG);
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if (pcie_port >= MAX_PCI_PORTS)
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return;
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/**
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* each pci port has two bits for mode and it starts at
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* bit 1. So use port number to get the right bit position.
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*/
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pcie_port <<= 1;
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val &= ~(DEVCFG_MODE_MASK << pcie_port);
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val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
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__raw_writel(val, KS2_DEVCFG);
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}
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int arch_cpu_init(void)
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{
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chip_configuration_unlock();
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@ -77,8 +105,13 @@ int arch_cpu_init(void)
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msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
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msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
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/* Initialize the PCIe-0 to work as Root Complex */
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config_pcie_mode(0, ROOTCOMPLEX);
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#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
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/* Initialize the PCIe-1 to work as Root Complex */
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config_pcie_mode(1, ROOTCOMPLEX);
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#endif
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#ifdef CONFIG_SOC_K2L
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osr_init();
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@ -144,6 +144,7 @@ typedef volatile unsigned int *dv_reg_p;
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#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
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#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
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#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
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#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
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/* PSC */
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#define KS2_PSC_BASE 0x02350000
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