reset: Add STi reset support
This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
Simon Glass
parent
0367bd4d60
commit
584861ffeb
@ -1132,6 +1132,7 @@ config ARCH_STI
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select DM_SERIAL
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select BLK
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select DM_MMC
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select DM_RESET
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help
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Support for STMicroelectronics STiH407/10 SoC family.
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This SoC is used on Linaro 96Board STiH410-B2260
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@ -20,6 +20,14 @@ config SANDBOX_RESET
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simply accepts requests to reset various HW modules without actually
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doing anything beyond a little error checking.
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config STI_RESET
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bool "Enable the STi reset"
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depends on ARCH_STI
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help
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Support for reset controllers on STMicroelectronics STiH407 family SoCs.
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Say Y if you want to control reset signals provided by system config
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block.
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config TEGRA_CAR_RESET
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bool "Enable Tegra CAR-based reset driver"
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depends on TEGRA_CAR
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@ -5,6 +5,7 @@
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obj-$(CONFIG_DM_RESET) += reset-uclass.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
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obj-$(CONFIG_STI_RESET) += sti-reset.o
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obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
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obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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320
drivers/reset/sti-reset.c
Normal file
320
drivers/reset/sti-reset.c
Normal file
@ -0,0 +1,320 @@
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/*
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* Copyright (c) 2017
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* Patrice Chotard <patrice.chotard@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/reset/stih407-resets.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sti_reset {
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const struct syscfg_reset_controller_data *data;
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};
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/**
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* Reset channel description for a system configuration register based
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* reset controller.
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*
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* @compatible: Compatible string of the syscon containing this
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* channel's control and ack (status) bits.
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* @reset_offset: Reset register offset in sysconf bank.
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* @reset_bit: Bit number in reset register.
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* @ack_offset: Ack reset register offset in syscon bank.
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* @ack_bit: Bit number in Ack reset register.
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*/
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struct syscfg_reset_channel_data {
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const char *compatible;
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int reset_offset;
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int reset_bit;
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int ack_offset;
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int ack_bit;
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};
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/**
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* Description of a system configuration register based reset controller.
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*
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* @wait_for_ack: The controller will wait for reset assert and de-assert to
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* be "ack'd" in a channel's ack field.
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* @active_low: Are the resets in this controller active low, i.e. clearing
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* the reset bit puts the hardware into reset.
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* @nr_channels: The number of reset channels in this controller.
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* @channels: An array of reset channel descriptions.
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*/
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struct syscfg_reset_controller_data {
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bool wait_for_ack;
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bool active_low;
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int nr_channels;
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const struct syscfg_reset_channel_data *channels;
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};
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/* STiH407 Peripheral powerdown definitions. */
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static const char stih407_core[] = "st,stih407-core-syscfg";
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static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
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static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
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#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
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{ .compatible = _c, \
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.reset_offset = _rr, \
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.reset_bit = _rb, \
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.ack_offset = _ar, \
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.ack_bit = _ab, }
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#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
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{ .compatible = _c, \
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.reset_offset = _rr, \
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.reset_bit = _rb, }
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#define STIH407_SRST_CORE(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
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#define STIH407_SRST_SBC(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
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#define STIH407_SRST_LPM(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
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#define STIH407_PDN_0(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
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#define STIH407_PDN_1(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
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#define STIH407_PDN_ETH(_bit, _stat) \
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_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
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/* Powerdown requests control 0 */
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#define SYSCFG_5000 0x0
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#define SYSSTAT_5500 0x7d0
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/* Powerdown requests control 1 (High Speed Links) */
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#define SYSCFG_5001 0x4
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#define SYSSTAT_5501 0x7d4
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/* Ethernet powerdown/status/reset */
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#define SYSCFG_4032 0x80
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#define SYSSTAT_4520 0x820
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#define SYSCFG_4002 0x8
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static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
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[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
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[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
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[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
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[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
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[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
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[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
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[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
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[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
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[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
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[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
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};
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/* Reset Generator control 0/1 */
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#define SYSCFG_5128 0x200
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#define SYSCFG_5131 0x20c
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#define SYSCFG_5132 0x210
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#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
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static const struct syscfg_reset_channel_data stih407_softresets[] = {
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[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
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[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
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[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
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[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
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[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
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[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
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[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
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[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
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[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
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[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
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[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
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[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
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[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
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[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
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[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
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[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
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[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
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[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
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[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
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[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
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[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
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[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
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[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
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[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
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[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
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[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
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[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
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[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
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[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
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[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
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[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
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[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
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[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
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};
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/* PicoPHY reset/control */
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#define SYSCFG_5061 0x0f4
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static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
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[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
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[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
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[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
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};
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static const struct
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syscfg_reset_controller_data stih407_powerdown_controller = {
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.wait_for_ack = true,
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.nr_channels = ARRAY_SIZE(stih407_powerdowns),
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.channels = stih407_powerdowns,
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};
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static const struct
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syscfg_reset_controller_data stih407_softreset_controller = {
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.wait_for_ack = false,
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.active_low = true,
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.nr_channels = ARRAY_SIZE(stih407_softresets),
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.channels = stih407_softresets,
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};
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static const struct
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syscfg_reset_controller_data stih407_picophyreset_controller = {
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.wait_for_ack = false,
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.nr_channels = ARRAY_SIZE(stih407_picophyresets),
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.channels = stih407_picophyresets,
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};
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phys_addr_t sti_reset_get_regmap(const char *compatible)
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{
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struct udevice *syscon;
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struct regmap *regmap;
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int node, ret;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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compatible);
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if (node < 0) {
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error("unable to find %s node\n", compatible);
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return node;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
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if (ret) {
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error("%s: uclass_get_device_by_of_offset failed: %d\n",
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__func__, ret);
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return ret;
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}
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regmap = syscon_get_regmap(syscon);
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if (!regmap) {
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error("unable to get regmap for %s\n", syscon->name);
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return -ENODEV;
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}
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return regmap->base;
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}
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static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
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{
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struct udevice *dev = reset_ctl->dev;
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struct syscfg_reset_controller_data *reset_desc =
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(struct syscfg_reset_controller_data *)(dev->driver_data);
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struct syscfg_reset_channel_data ch;
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phys_addr_t base;
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u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
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void __iomem *reg;
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/* check if reset id is inside available range */
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if (reset_ctl->id >= reset_desc->nr_channels)
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return -EINVAL;
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/* get reset sysconf register base address */
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base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
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ch = reset_desc->channels[reset_ctl->id];
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reg = (void __iomem *)base + ch.reset_offset;
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if (ctrl_val)
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generic_set_bit(ch.reset_bit, reg);
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else
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generic_clear_bit(ch.reset_bit, reg);
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if (!reset_desc->wait_for_ack)
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return 0;
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reg = (void __iomem *)base + ch.ack_offset;
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if (wait_for_bit(__func__, reg, BIT(ch.ack_bit), ctrl_val,
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1000, false)) {
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error("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
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reset_ctl, reset_ctl->dev, reset_ctl->id);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int sti_reset_request(struct reset_ctl *reset_ctl)
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{
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return 0;
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}
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static int sti_reset_free(struct reset_ctl *reset_ctl)
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{
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return 0;
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}
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static int sti_reset_assert(struct reset_ctl *reset_ctl)
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{
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return sti_reset_program_hw(reset_ctl, true);
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}
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static int sti_reset_deassert(struct reset_ctl *reset_ctl)
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{
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return sti_reset_program_hw(reset_ctl, false);
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}
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struct reset_ops sti_reset_ops = {
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.request = sti_reset_request,
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.free = sti_reset_free,
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.rst_assert = sti_reset_assert,
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.rst_deassert = sti_reset_deassert,
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};
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static int sti_reset_probe(struct udevice *dev)
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{
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struct sti_reset *priv = dev_get_priv(dev);
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priv->data = (void *)dev_get_driver_data(dev);
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return 0;
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}
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static const struct udevice_id sti_reset_ids[] = {
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{
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.compatible = "st,stih407-picophyreset",
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.data = (ulong)&stih407_picophyreset_controller,
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},
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{
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.compatible = "st,stih407-powerdown",
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.data = (ulong)&stih407_powerdown_controller,
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},
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{
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.compatible = "st,stih407-softreset",
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.data = (ulong)&stih407_softreset_controller,
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},
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{ }
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};
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U_BOOT_DRIVER(sti_reset) = {
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.name = "sti_reset",
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.id = UCLASS_RESET,
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.of_match = sti_reset_ids,
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.probe = sti_reset_probe,
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.priv_auto_alloc_size = sizeof(struct sti_reset),
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.ops = &sti_reset_ops,
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};
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