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83xx, uec: split enet_interface in two variables

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There's no sensible reason to unite speed and interface type into
one variable.  So split this variable enet_interface into two
vars: enet_interface_type, which hold the interface type and speed.

Also: add the possibility for switching between 10 and 100 MBit
interfaces on the fly, when running in FAST_ETH mode.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Heiko Schocher 2010-01-20 09:04:28 +01:00 committed by Ben Warren
parent d7e354374c
commit 582c55a027
11 changed files with 175 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -159,7 +159,8 @@ int board_eth_init(bd_t *bd)
int i; int i;
for (i = 0; i < ARRAY_SIZE(uec_info); i++) for (i = 0; i < ARRAY_SIZE(uec_info); i++)
uec_info[i].enet_interface = ENET_1000_RGMII_RXID; uec_info[i].enet_interface_type = RGMII_RXID;
uec_info[i].speed = 1000;
} }
return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
} }

122
drivers/qe/uec.c
View File

@ -323,9 +323,10 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
return 0; return 0;
} }
static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) static int uec_set_mac_if_mode(uec_private_t *uec,
enet_interface_type_e if_mode, int speed)
{ {
enet_interface_e enet_if_mode; enet_interface_type_e enet_if_mode;
uec_info_t *uec_info; uec_info_t *uec_info;
uec_t *uec_regs; uec_t *uec_regs;
u32 upsmr; u32 upsmr;
@ -346,52 +347,68 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
upsmr = in_be32(&uec->uccf->uf_regs->upsmr); upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
switch (enet_if_mode) { switch (speed) {
case ENET_100_MII: case 10:
case ENET_10_MII:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
switch (enet_if_mode) {
case MII:
break;
case RGMII:
upsmr |= (UPSMR_RPM | UPSMR_R10M);
break;
case RMII:
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
default:
return -EINVAL;
break;
}
break; break;
case ENET_1000_GMII: case 100:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
break;
case ENET_1000_TBI:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
upsmr |= UPSMR_TBIM;
break;
case ENET_1000_RTBI:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
upsmr |= (UPSMR_RPM | UPSMR_TBIM);
break;
case ENET_1000_RGMII_RXID:
case ENET_1000_RGMII_ID:
case ENET_1000_RGMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
upsmr |= UPSMR_RPM;
break;
case ENET_100_RGMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= UPSMR_RPM; switch (enet_if_mode) {
case MII:
break;
case RGMII:
upsmr |= UPSMR_RPM;
break;
case RMII:
upsmr |= UPSMR_RMM;
break;
default:
return -EINVAL;
break;
}
break; break;
case ENET_10_RGMII: case 1000:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_RPM | UPSMR_R10M);
break;
case ENET_100_RMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= UPSMR_RMM;
break;
case ENET_10_RMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
case ENET_1000_SGMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
upsmr |= UPSMR_SGMM; switch (enet_if_mode) {
case GMII:
break;
case TBI:
upsmr |= UPSMR_TBIM;
break;
case RTBI:
upsmr |= (UPSMR_RPM | UPSMR_TBIM);
break;
case RGMII_RXID:
case RGMII_ID:
case RGMII:
upsmr |= UPSMR_RPM;
break;
case SGMII:
upsmr |= UPSMR_SGMM;
break;
default:
return -EINVAL;
break;
}
break; break;
default: default:
return -EINVAL; return -EINVAL;
break; break;
} }
out_be32(&uec_regs->maccfg2, maccfg2); out_be32(&uec_regs->maccfg2, maccfg2);
out_be32(&uec->uccf->uf_regs->upsmr, upsmr); out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
@ -504,7 +521,7 @@ static void adjust_link(struct eth_device *dev)
struct uec_mii_info *mii_info = uec->mii_info; struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev, extern void change_phy_interface_mode(struct eth_device *dev,
enet_interface_e mode); enet_interface_type_e mode, int speed);
uec_regs = uec->uec_regs; uec_regs = uec->uec_regs;
if (mii_info->link) { if (mii_info->link) {
@ -522,25 +539,19 @@ static void adjust_link(struct eth_device *dev)
} }
if (mii_info->speed != uec->oldspeed) { if (mii_info->speed != uec->oldspeed) {
enet_interface_type_e mode = \
uec->uec_info->enet_interface_type;
if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
switch (mii_info->speed) { switch (mii_info->speed) {
case 1000: case 1000:
break; break;
case 100: case 100:
printf ("switching to rgmii 100\n"); printf ("switching to rgmii 100\n");
/* change phy to rgmii 100 */ mode = RGMII;
change_phy_interface_mode(dev,
ENET_100_RGMII);
/* change the MAC interface mode */
uec_set_mac_if_mode(uec,ENET_100_RGMII);
break; break;
case 10: case 10:
printf ("switching to rgmii 10\n"); printf ("switching to rgmii 10\n");
/* change phy to rgmii 10 */ mode = RGMII;
change_phy_interface_mode(dev,
ENET_10_RGMII);
/* change the MAC interface mode */
uec_set_mac_if_mode(uec,ENET_10_RGMII);
break; break;
default: default:
printf("%s: Ack,Speed(%d)is illegal\n", printf("%s: Ack,Speed(%d)is illegal\n",
@ -549,6 +560,11 @@ static void adjust_link(struct eth_device *dev)
} }
} }
/* change phy */
change_phy_interface_mode(dev, mode, mii_info->speed);
/* change the MAC interface mode */
uec_set_mac_if_mode(uec, mode, mii_info->speed);
printf("%s: Speed %dBT\n", dev->name, mii_info->speed); printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
uec->oldspeed = mii_info->speed; uec->oldspeed = mii_info->speed;
} }
@ -980,7 +996,6 @@ static int uec_startup(uec_private_t *uec)
int num_threads_tx; int num_threads_tx;
int num_threads_rx; int num_threads_rx;
u32 utbipar; u32 utbipar;
enet_interface_e enet_interface;
u32 length; u32 length;
u32 align; u32 align;
qe_bd_t *bd; qe_bd_t *bd;
@ -1060,7 +1075,7 @@ static int uec_startup(uec_private_t *uec)
out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
/* Setup MAC interface mode */ /* Setup MAC interface mode */
uec_set_mac_if_mode(uec, uec_info->enet_interface); uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
/* Setup MII management base */ /* Setup MII management base */
#ifndef CONFIG_eTSEC_MDIO_BUS #ifndef CONFIG_eTSEC_MDIO_BUS
@ -1075,7 +1090,6 @@ static int uec_startup(uec_private_t *uec)
/* Setup UTBIPAR */ /* Setup UTBIPAR */
utbipar = in_be32(&uec_regs->utbipar); utbipar = in_be32(&uec_regs->utbipar);
utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
enet_interface = uec->uec_info->enet_interface;
/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
* This frees up the remaining SMI addresses for use. * This frees up the remaining SMI addresses for use.
@ -1084,7 +1098,8 @@ static int uec_startup(uec_private_t *uec)
out_be32(&uec_regs->utbipar, utbipar); out_be32(&uec_regs->utbipar, utbipar);
/* Configure the TBI for SGMII operation */ /* Configure the TBI for SGMII operation */
if (uec->uec_info->enet_interface == ENET_1000_SGMII) { if ((uec->uec_info->enet_interface_type == SGMII) &&
(uec->uec_info->speed == 1000)) {
uec_write_phy_reg(uec->dev, uec_regs->utbipar, uec_write_phy_reg(uec->dev, uec_regs->utbipar,
ENET_TBI_MII_ANA, TBIANA_SETTINGS); ENET_TBI_MII_ANA, TBIANA_SETTINGS);
@ -1215,6 +1230,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
if (err || i <= 0) if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name); printf("warning: %s: timeout on PHY link\n", dev->name);
adjust_link(dev);
uec->the_first_run = 1; uec->the_first_run = 1;
} }

34
drivers/qe/uec.h
View File

@ -662,22 +662,18 @@ typedef enum uec_num_of_threads {
/* UEC ethernet interface type /* UEC ethernet interface type
*/ */
typedef enum enet_interface { typedef enum enet_interface_type {
ENET_10_MII, MII,
ENET_10_RMII, RMII,
ENET_10_RGMII, RGMII,
ENET_100_MII, GMII,
ENET_100_RMII, RGMII_ID,
ENET_100_RGMII, RGMII_RXID,
ENET_1000_GMII, RGMII_TXID,
ENET_1000_RGMII, TBI,
ENET_1000_RGMII_ID, RTBI,
ENET_1000_RGMII_RXID, SGMII
ENET_1000_RGMII_TXID, } enet_interface_type_e;
ENET_1000_TBI,
ENET_1000_RTBI,
ENET_1000_SGMII
} enet_interface_e;
/* UEC initialization info struct /* UEC initialization info struct
*/ */
@ -696,7 +692,8 @@ typedef enum enet_interface {
.tx_bd_ring_len = 16, \ .tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \
.phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
.enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \ .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
.speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
} }
typedef struct uec_info { typedef struct uec_info {
@ -708,7 +705,8 @@ typedef struct uec_info {
u16 rx_bd_ring_len; u16 rx_bd_ring_len;
u16 tx_bd_ring_len; u16 tx_bd_ring_len;
u8 phy_address; u8 phy_address;
enet_interface_e enet_interface; enet_interface_type_e enet_interface_type;
int speed;
} uec_info_t; } uec_info_t;
/* UEC driver initialized info /* UEC driver initialized info

84
drivers/qe/uec_phy.c
View File

@ -401,7 +401,8 @@ static int bcm_init(struct uec_mii_info *mii_info)
gbit_config_aneg(mii_info); gbit_config_aneg(mii_info);
if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) { if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
(uec->uec_info->speed == 1000)) {
u16 val; u16 val;
int cnt = 50; int cnt = 50;
@ -429,20 +430,22 @@ static int marvell_init(struct uec_mii_info *mii_info)
{ {
struct eth_device *edev = mii_info->dev; struct eth_device *edev = mii_info->dev;
uec_private_t *uec = edev->priv; uec_private_t *uec = edev->priv;
enum enet_interface iface = uec->uec_info->enet_interface; enum enet_interface_type iface = uec->uec_info->enet_interface_type;
int speed = uec->uec_info->speed;
if (iface == ENET_1000_RGMII_ID || if ((speed == 1000) &&
iface == ENET_1000_RGMII_RXID || (iface == RGMII_ID ||
iface == ENET_1000_RGMII_TXID) { iface == RGMII_RXID ||
iface == RGMII_TXID)) {
int temp; int temp;
temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
if (iface == ENET_1000_RGMII_ID) { if (iface == RGMII_ID) {
temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
} else if (iface == ENET_1000_RGMII_RXID) { } else if (iface == RGMII_RXID) {
temp &= ~MII_M1111_TX_DELAY; temp &= ~MII_M1111_TX_DELAY;
temp |= MII_M1111_RX_DELAY; temp |= MII_M1111_RX_DELAY;
} else if (iface == ENET_1000_RGMII_TXID) { } else if (iface == RGMII_TXID) {
temp &= ~MII_M1111_RX_DELAY; temp &= ~MII_M1111_RX_DELAY;
temp |= MII_M1111_TX_DELAY; temp |= MII_M1111_TX_DELAY;
} }
@ -795,7 +798,9 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
} }
void marvell_phy_interface_mode (struct eth_device *dev, void marvell_phy_interface_mode (struct eth_device *dev,
enet_interface_e mode) enet_interface_type_e type,
int speed
)
{ {
uec_private_t *uec = (uec_private_t *) dev->priv; uec_private_t *uec = (uec_private_t *) dev->priv;
struct uec_mii_info *mii_info; struct uec_mii_info *mii_info;
@ -807,33 +812,35 @@ void marvell_phy_interface_mode (struct eth_device *dev,
} }
mii_info = uec->mii_info; mii_info = uec->mii_info;
if (mode == ENET_100_RGMII) { if (type == RGMII) {
phy_write (mii_info, 0x00, 0x9140); if (speed == 100) {
phy_write (mii_info, 0x1d, 0x001f); phy_write (mii_info, 0x00, 0x9140);
phy_write (mii_info, 0x1e, 0x200c); phy_write (mii_info, 0x1d, 0x001f);
phy_write (mii_info, 0x1d, 0x0005); phy_write (mii_info, 0x1e, 0x200c);
phy_write (mii_info, 0x1e, 0x0000); phy_write (mii_info, 0x1d, 0x0005);
phy_write (mii_info, 0x1e, 0x0100); phy_write (mii_info, 0x1e, 0x0000);
phy_write (mii_info, 0x09, 0x0e00); phy_write (mii_info, 0x1e, 0x0100);
phy_write (mii_info, 0x04, 0x01e1); phy_write (mii_info, 0x09, 0x0e00);
phy_write (mii_info, 0x00, 0x9140); phy_write (mii_info, 0x04, 0x01e1);
phy_write (mii_info, 0x00, 0x1000); phy_write (mii_info, 0x00, 0x9140);
udelay (100000); phy_write (mii_info, 0x00, 0x1000);
phy_write (mii_info, 0x00, 0x2900); udelay (100000);
phy_write (mii_info, 0x14, 0x0cd2); phy_write (mii_info, 0x00, 0x2900);
phy_write (mii_info, 0x00, 0xa100); phy_write (mii_info, 0x14, 0x0cd2);
phy_write (mii_info, 0x09, 0x0000); phy_write (mii_info, 0x00, 0xa100);
phy_write (mii_info, 0x1b, 0x800b); phy_write (mii_info, 0x09, 0x0000);
phy_write (mii_info, 0x04, 0x05e1); phy_write (mii_info, 0x1b, 0x800b);
phy_write (mii_info, 0x00, 0xa100); phy_write (mii_info, 0x04, 0x05e1);
phy_write (mii_info, 0x00, 0x2100); phy_write (mii_info, 0x00, 0xa100);
udelay (1000000); phy_write (mii_info, 0x00, 0x2100);
} else if (mode == ENET_10_RGMII) { udelay (1000000);
phy_write (mii_info, 0x14, 0x8e40); } else if (speed == 10) {
phy_write (mii_info, 0x1b, 0x800b); phy_write (mii_info, 0x14, 0x8e40);
phy_write (mii_info, 0x14, 0x0c82); phy_write (mii_info, 0x1b, 0x800b);
phy_write (mii_info, 0x00, 0x8100); phy_write (mii_info, 0x14, 0x0c82);
udelay (1000000); phy_write (mii_info, 0x00, 0x8100);
udelay (1000000);
}
} }
/* handle 88e1111 rev.B2 erratum 5.6 */ /* handle 88e1111 rev.B2 erratum 5.6 */
@ -844,9 +851,10 @@ void marvell_phy_interface_mode (struct eth_device *dev,
/* now the B2 will correctly report autoneg completion status */ /* now the B2 will correctly report autoneg completion status */
} }
void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode) void change_phy_interface_mode (struct eth_device *dev,
enet_interface_type_e type, int speed)
{ {
#ifdef CONFIG_PHY_MODE_NEED_CHANGE #ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode (dev, mode); marvell_phy_interface_mode (dev, type, speed);
#endif #endif
} }

6
include/configs/MPC8323ERDB.h
View File

@ -347,7 +347,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 4 #define CONFIG_SYS_UEC1_PHY_ADDR 4
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII #define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif #endif
#define CONFIG_UEC_ETH2 /* ETH4 */ #define CONFIG_UEC_ETH2 /* ETH4 */
@ -358,7 +359,8 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0 #define CONFIG_SYS_UEC2_PHY_ADDR 0
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII #define CONFIG_SYS_UEC2_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif #endif
/* /*

6
include/configs/MPC832XEMDS.h
View File

@ -362,7 +362,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 3 #define CONFIG_SYS_UEC1_PHY_ADDR 3
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII #define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif #endif
#define CONFIG_UEC_ETH2 /* ETH4 */ #define CONFIG_UEC_ETH2 /* ETH4 */
@ -373,7 +374,8 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4 #define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII #define CONFIG_SYS_UEC2_INTERFACE_TYPE MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif #endif
/* /*

6
include/configs/MPC8360EMDS.h
View File

@ -400,7 +400,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif #endif
#define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_UEC_ETH2 /* GETH2 */
@ -411,7 +412,8 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif #endif
/* /*

6
include/configs/MPC8360ERDK.h
View File

@ -318,7 +318,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2 #define CONFIG_SYS_UEC1_PHY_ADDR 2
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif #endif
#define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_UEC_ETH2 /* GETH2 */
@ -329,7 +330,8 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4 #define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif #endif
/* /*

6
include/configs/MPC8568MDS.h
View File

@ -333,7 +333,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7 #define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif #endif
#define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_UEC_ETH2 /* GETH2 */
@ -344,7 +345,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif #endif
#endif /* CONFIG_QE */ #endif /* CONFIG_QE */

30
include/configs/MPC8569MDS.h
View File

@ -326,12 +326,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7 #define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE) #elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH1 */ #endif /* CONFIG_UEC_ETH1 */
@ -345,12 +347,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE) #elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH2 */ #endif /* CONFIG_UEC_ETH2 */
@ -364,12 +368,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 2 #define CONFIG_SYS_UEC3_PHY_ADDR 2
#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE) #elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH3 */ #endif /* CONFIG_UEC_ETH3 */
@ -383,12 +389,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 3 #define CONFIG_SYS_UEC4_PHY_ADDR 3
#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE) #elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH4 */ #endif /* CONFIG_UEC_ETH4 */
@ -401,7 +409,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC6_PHY_ADDR 4 #define CONFIG_SYS_UEC6_PHY_ADDR 4
#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH6 */ #endif /* CONFIG_UEC_ETH6 */
#undef CONFIG_UEC_ETH8 /* GETH8 */ #undef CONFIG_UEC_ETH8 /* GETH8 */
@ -413,7 +422,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC8_PHY_ADDR 6 #define CONFIG_SYS_UEC8_PHY_ADDR 6
#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH8 */ #endif /* CONFIG_UEC_ETH8 */
#endif /* CONFIG_QE */ #endif /* CONFIG_QE */

3
include/configs/kmeter1.h
View File

@ -295,7 +295,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif #endif
/* /*