mx6sl: Add initial support for mx6slevk board
mx6slevk board is a development board from Freescale based on the mx6 solo-lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
25b4aa146a
commit
57ca432fb9
@ -664,6 +664,7 @@ Fabio Estevam <fabio.estevam@freescale.com>
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mx6qsabresd i.MX6Q
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mx6qsabreauto i.MX6Q
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wandboard i.MX6DL/S
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mx6slevk i.MX6SL
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Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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28
board/freescale/mx6slevk/Makefile
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28
board/freescale/mx6slevk/Makefile
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@ -0,0 +1,28 @@
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# (C) Copyright 2013 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := mx6slevk.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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118
board/freescale/mx6slevk/imximage.cfg
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118
board/freescale/mx6slevk/imximage.cfg
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@ -0,0 +1,118 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License or (at your option) any later version.
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020c4018 0x00260324
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020e0344 0x00003030
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DATA 4 0x020e0348 0x00003030
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DATA 4 0x020e034c 0x00003030
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DATA 4 0x020e0350 0x00003030
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DATA 4 0x020e030c 0x00000030
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DATA 4 0x020e0310 0x00000030
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DATA 4 0x020e0314 0x00000030
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DATA 4 0x020e0318 0x00000030
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DATA 4 0x020e0300 0x00000030
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DATA 4 0x020e031c 0x00000030
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e0320 0x00000030
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DATA 4 0x020e032c 0x00000000
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DATA 4 0x020e033c 0x00000008
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DATA 4 0x020e0340 0x00000008
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DATA 4 0x020e05c4 0x00000030
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DATA 4 0x020e05cc 0x00000030
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DATA 4 0x020e05d4 0x00000030
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DATA 4 0x020e05d8 0x00000030
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DATA 4 0x020e05ac 0x00000030
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DATA 4 0x020e05c8 0x00000030
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DATA 4 0x020e05b0 0x00020000
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DATA 4 0x020e05b4 0x00000000
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DATA 4 0x020e05c0 0x00020000
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DATA 4 0x020e05d0 0x00080000
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b085c 0x1b4700c7
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b0890 0x00300000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b082c 0xf3333333
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DATA 4 0x021b0830 0xf3333333
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DATA 4 0x021b0834 0xf3333333
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DATA 4 0x021b0838 0xf3333333
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DATA 4 0x021b0848 0x4241444a
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DATA 4 0x021b0850 0x3030312b
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x00000000
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DATA 4 0x021b08c0 0x24911492
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b000c 0x33374133
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DATA 4 0x021b0004 0x00020024
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DATA 4 0x021b0010 0x00100A82
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DATA 4 0x021b0014 0x00000093
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DATA 4 0x021b0018 0x00001688
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DATA 4 0x021b002c 0x0f9f26d2
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DATA 4 0x021b0030 0x0000020e
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DATA 4 0x021b0038 0x00190778
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DATA 4 0x021b0008 0x00000000
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DATA 4 0x021b0040 0x0000004f
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DATA 4 0x021b0000 0xc3110000
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DATA 4 0x021b001c 0x003f8030
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DATA 4 0x021b001c 0xff0a8030
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DATA 4 0x021b001c 0x82018030
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DATA 4 0x021b001c 0x04028030
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DATA 4 0x021b001c 0x02038030
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DATA 4 0x021b001c 0xff0a8038
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DATA 4 0x021b001c 0x82018038
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DATA 4 0x021b001c 0x04028038
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DATA 4 0x021b001c 0x02038038
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DATA 4 0x021b0800 0xa1310003
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DATA 4 0x021b0020 0x00001800
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DATA 4 0x021b0818 0x00000000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b0004 0x00025564
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x021b001c 0x00000000
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102
board/freescale/mx6slevk/mx6slevk.c
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102
board/freescale/mx6slevk/mx6slevk.c
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@ -0,0 +1,102 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC2_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1; /* Assume boot SD always present */
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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u32 get_board_rev(void)
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{
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return get_cpu_rev();
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}
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int checkboard(void)
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{
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puts("Board: MX6SLEVK\n");
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return 0;
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}
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@ -259,6 +259,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
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mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
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mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
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mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
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mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
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eco5pk arm armv7 eco5pk 8dtech omap3
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nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
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nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
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189
include/configs/mx6slevk.h
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189
include/configs/mx6slevk.h
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@ -0,0 +1,189 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6SL EVK board.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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#include <asm/sizes.h>
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#define CONFIG_MX6
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define MACH_TYPE_MX6SLEVK 4307
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#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_MXC_GPIO
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
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/* MMC Configs */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* Command definition */
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_IMLS
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_LOADADDR 0x80800000
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#define CONFIG_SYS_TEXT_BASE 0x87800000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=uImage\0" \
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"console=ttymxc0\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_file=imx6sl-evk.dtb\0" \
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"fdt_addr=0x81000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"mmcdev=0\0" \
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"mmcpart=2\0" \
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"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootm ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootm; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootm; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${uimage}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"bootm ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootm; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootm; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev};" \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "=> "
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||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_STACKSIZE SZ_128K
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user