rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
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assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
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assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
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hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
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assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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