powerpc/85xx: Add P1023RDB board support
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Chunhe Lan
Andy Fleming
parent
bd7c023e48
commit
5707233880
@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
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COBJS-$(CONFIG_P1020) += ddr-gen3.o
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COBJS-$(CONFIG_P1021) += ddr-gen3.o
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COBJS-$(CONFIG_P1022) += ddr-gen3.o
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COBJS-$(CONFIG_P1023) += ddr-gen3.o
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COBJS-$(CONFIG_P1024) += ddr-gen3.o
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COBJS-$(CONFIG_P1025) += ddr-gen3.o
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COBJS-$(CONFIG_P2010) += ddr-gen3.o
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33
board/freescale/p1023rdb/Makefile
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33
board/freescale/p1023rdb/Makefile
Normal file
@ -0,0 +1,33 @@
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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105
board/freescale/p1023rdb/ddr.c
Normal file
105
board/freescale/p1023rdb/ddr.c
Normal file
@ -0,0 +1,105 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* CONFIG_SYS_DDR_RAW_TIMING */
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/*
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* Hynix H5TQ1G83TFR-H9C
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*/
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 536870912u,
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.capacity = 536870912u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 14,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1875,
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.caslat_X = 0x1e << 4, /* 5,6,7,8 */
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.tAA_ps = 13125,
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.tWR_ps = 18000,
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.tRCD_ps = 13125,
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.tRRD_ps = 7500,
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.tRP_ps = 13125,
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.tRAS_ps = 37500,
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.tRC_ps = 50625,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 37500,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR on board";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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int i;
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popts->clk_adjust = 6;
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popts->cpo_override = 0x1f;
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popts->write_data_delay = 2;
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x8;
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popts->trwt_override = 1;
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popts->trwt = 0;
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
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popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
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}
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}
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34
board/freescale/p1023rdb/law.c
Normal file
34
board/freescale/p1023rdb/law.c
Normal file
@ -0,0 +1,34 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
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LAW_TRGT_IF_DPAA_SWP_SRAM),
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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161
board/freescale/p1023rdb/p1023rdb.c
Normal file
161
board/freescale/p1023rdb/p1023rdb.c
Normal file
@ -0,0 +1,161 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Authors: Roy Zang <tie-fei.zang@freescale.com>
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* Chunhe Lan <Chunhe.Lan@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_portals.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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/* Set ABSWP to implement conversion of addresses in the LBC */
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setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: P1023 RDB\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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setup_portals();
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return 0;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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return gd->bus_clk;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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return gd->mem_clk;
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}
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int board_eth_init(bd_t *bis)
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{
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ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_pq_mdio_info dtsec_mdio_info;
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/*
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* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
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* is not correct.
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*/
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_mdio(FM1_DTSEC1,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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fm_info_set_mdio(FM1_DTSEC2,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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#ifdef CONFIG_FMAN_ENET
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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fdt_fixup_fman_ethernet(blob);
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}
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#endif
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115
board/freescale/p1023rdb/tlb.c
Normal file
115
board/freescale/p1023rdb/tlb.c
Normal file
@ -0,0 +1,115 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
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0, 0, BOOKE_PAGESZ_4K, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_4M, 1),
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/* W**G* - Flash, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
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CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 9, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_16K, 1),
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 12, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 13, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -831,6 +831,7 @@ P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freesca
|
||||
P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD
|
||||
P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD
|
||||
P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT
|
||||
P1023RDB powerpc mpc85xx p1023rdb freescale - P1023RDB
|
||||
P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS
|
||||
P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND
|
||||
P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB
|
||||
|
||||
401
include/configs/P1023RDB.h
Normal file
401
include/configs/P1023RDB.h
Normal file
@ -0,0 +1,401 @@
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Authors: Roy Zang <tie-fei.zang@freescale.com>
|
||||
* Chunhe Lan <Chunhe.Lan@freescale.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE /* BOOKE */
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx
|
||||
#define CONFIG_P1023
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_clock_freq(void);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x02000000
|
||||
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/* Implement conversion of addresses in the LBC */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_FSL_DDR3
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE
|
||||
#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x50
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x1fff_ffff DDR 512M cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
|
||||
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
|
||||
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
|
||||
* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
|
||||
* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
|
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
|
||||
*
|
||||
* Localbus non-cacheable
|
||||
*
|
||||
* 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
|
||||
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
|
||||
*/
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
|
||||
| OR_FCM_PGS \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
*/
|
||||
#define CONFIG_ID_EEPROM
|
||||
#ifdef CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 3, Slot 1, tgtid 3, Base address b000 */
|
||||
#define CONFIG_SYS_PCIE3_NAME "Slot 3"
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_NAME "Slot 2"
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 1, Slot 2, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "Slot 1"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Qman/Bman */
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
|
||||
/* For FM */
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#endif
|
||||
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
/* QE microcode/firmware address */
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
|
||||
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
|
||||
|
||||
#define CONFIG_SYS_TBIPA_VALUE 8
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user