spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig

This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-30 18:07:23 -04:00 · 2022-03-30 18:07:23 -04:00 · 55b3ba4c2b
commit 55b3ba4c2b
parent 5d14c336b2
21 changed files with 35 additions and 29 deletions
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@ -16,6 +16,7 @@
 #include <errno.h>
 #include <init.h>
 #include <log.h>
+#include <mach/clock_manager.h>

 DECLARE_GLOBAL_DATA_PTR;

--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@ -134,6 +134,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@ -127,6 +127,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@ -145,6 +145,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@ -114,6 +114,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@ -181,6 +181,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@ -138,6 +138,8 @@ CONFIG_SOC_TI=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@ -89,6 +89,8 @@ CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
 CONFIG_DAVINCI_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@ -73,6 +73,8 @@ CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
 CONFIG_DAVINCI_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@ -39,3 +39,5 @@ CONFIG_PHY_RESET_DELAY=10000
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=3000000
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@ -128,6 +128,14 @@ config CADENCE_QSPI
 	  used to access the SPI NOR flash on platforms embedding this
 	  Cadence IP core.

+config HAS_CQSPI_REF_CLK
+	bool "Cadence QSPI static reference clock"
+	depends on CADENCE_QSPI
+
+config CQSPI_REF_CLK
+	int "Cadence QSPI reference clock value in Hz"
+	depends on HAS_CQSPI_REF_CLK
+
 config CF_SPI
        bool "ColdFire SPI driver"
        help
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@ -188,8 +188,10 @@ static int cadence_spi_probe(struct udevice *bus)
 	if (plat->ref_clk_hz == 0) {
 		ret = clk_get_by_index(bus, 0, &clk);
 		if (ret) {
-#ifdef CONFIG_CQSPI_REF_CLK
+#ifdef CONFIG_HAS_CQSPI_REF_CLK
 			plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#elif defined(CONFIG_ARCH_SOCFPGA)
+			plat->ref_clk_hz = cm_get_qspi_controller_clk_hz();
 #else
 			return ret;
 #endif
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@ -95,5 +95,6 @@ void cadence_qspi_apb_delay(void *reg_base,
 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
 void cadence_qspi_apb_readdata_capture(void *reg_base,
 	unsigned int bypass, unsigned int delay);
+unsigned int cm_get_qspi_controller_clk_hz(void);

 #endif /* __CADENCE_QSPI_H__ */
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@ -57,7 +57,6 @@
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE

 #define CONFIG_SYS_BOOTM_LEN		SZ_64M
-#define CONFIG_CQSPI_REF_CLK		133333333

 /* HyperFlash related configuration */

--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@ -58,7 +58,6 @@
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE

 #define CONFIG_SYS_BOOTM_LEN		SZ_64M
-#define CONFIG_CQSPI_REF_CLK		133333333

 /* U-Boot general configuration */
 #define EXTRA_ENV_J721S2_BOARD_SETTINGS					\
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@ -59,10 +59,6 @@
 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 #define PHY_ANEG_TIMEOUT	10000 /* PHY needs longer aneg time */

-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CQSPI_REF_CLK 384000000
-#endif
-
 #define SPI_MTD_PARTS	KEYSTONE_SPI1_MTD_PARTS

 #include <configs/ti_armv7_keystone2.h>
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@ -121,15 +121,6 @@
 #define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
 #endif

-/*
- * QSPI support
- */
-/* QSPI reference clock */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
-#endif
-
 /*
 * USB
 */
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@ -61,11 +61,6 @@
 #define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
 #endif /* CONFIG_SPL_BUILD */

-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
-#endif
-
 #endif /* CONFIG_CADENCE_QSPI */

 /*
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@ -31,12 +31,4 @@

 /* Misc configuration */

-/*
-+ * QSPI support
-+ */
-#ifdef CONFIG_OF_CONTROL		/* QSPI is controlled via DT */
-#define CONFIG_CQSPI_REF_CLK		((30/4)/2)*1000*1000
-
-#endif
-
 #endif /* __CONFIG_H */