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- Sync DT with Linux 5.2-rc1 for G12A

Browse Source 
- Add USB clock support that was introduced in 5.2-rc1 bindings
 - Add currently in-review for Linux eMMC & USB DT for G12A in -u-boot.dtsi
 - Fix PHY routing to external PHY when chainloading from a misconfigred bootloader
 - Remove useless PHY GPIO reset from q200 board file
 - Enable USB support for Amlogic U200 reference board
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Merge tag 'u-boot-amlogic-20190531' of git://git.denx.de/u-boot-amlogic

- Sync DT with Linux 5.2-rc1 for G12A
- Add USB clock support that was introduced in 5.2-rc1 bindings
- Add currently in-review for Linux eMMC & USB DT for G12A in -u-boot.dtsi
- Fix PHY routing to external PHY when chainloading from a misconfigred bootloader
- Remove useless PHY GPIO reset from q200 board file
- Enable USB support for Amlogic U200 reference board
This commit is contained in:
Tom Rini 2019-05-31 07:16:28 -04:00
commit 55955427cb
11 changed files with 1034 additions and 12 deletions
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216
arch/arm/dts/meson-g12a-u-boot.dtsi Normal file
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@ -0,0 +1,216 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/ {
soc {
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000
0x0 0xff634540 0x0 0x8>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
status = "disabled";
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
sd_emmc_a: sd@ffe03000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe03000 0x0 0x800>;
interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
};
sd_emmc_b: sd@ffe05000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_c: mmc@ffe07000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe07000 0x0 0x800>;
interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
};
};
&periphs_pinctrl {
emmc_pins: emmc {
mux {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_clk",
"emmc_cmd";
function = "emmc";
bias-pull-up;
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_nand_ds";
function = "emmc";
bias-pull-down;
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "BOOT_8";
function = "gpio_periphs";
bias-pull-down;
};
};
eth_leds_pins: eth-leds {
mux {
groups = "eth_link_led",
"eth_act_led";
function = "eth";
bias-disable;
};
};
eth_rmii_pins: eth-rmii {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_rgmii_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_txen",
"eth_txd0",
"eth_txd1";
function = "eth";
bias-disable;
};
};
eth_rgmii_pins: eth-rgmii {
mux {
groups = "eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
bias-disable;
};
};
sdcard_c_pins: sdcard_c {
mux {
groups = "sdcard_d0_c",
"sdcard_d1_c",
"sdcard_d2_c",
"sdcard_d3_c",
"sdcard_cmd_c",
"sdcard_clk_c";
function = "sdcard";
bias-pull-up;
};
};
sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
mux {
groups = "GPIOC_4";
function = "gpio_periphs";
bias-pull-down;
};
};
sdcard_z_pins: sdcard_z {
mux {
groups = "sdcard_d0_z",
"sdcard_d1_z",
"sdcard_d2_z",
"sdcard_d3_z",
"sdcard_cmd_z",
"sdcard_clk_z";
function = "sdcard";
bias-pull-up;
};
};
sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
mux {
groups = "GPIOZ_6";
function = "gpio_periphs";
bias-pull-down;
};
};
};
&periphs {
eth_phy: mdio-multiplexer@4c000 {
compatible = "amlogic,g12a-mdio-mux";
reg = <0x0 0x4c000 0x0 0xa4>;
clocks = <&clkc CLKID_ETH_PHY>,
<&xtal>,
<&clkc CLKID_MPLL_5OM>;
clock-names = "pclk", "clkin0", "clkin1";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
ext_mdio: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
int_mdio: mdio@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
compatible = "ethernet-phy-id0180.3300",
"ethernet-phy-ieee802.3-c22";
reg = <8>;
max-speed = <100>;
/* FIXME: Add irq support */
};
};
};
};

63
arch/arm/dts/meson-g12a-u200-u-boot.dtsi Normal file
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@ -0,0 +1,63 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-g12a-u-boot.dtsi"
/ {
aliases {
ethernet0 = &ethmac;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_leds_pins>;
pinctrl-names = "default";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};

147
arch/arm/dts/meson-g12a-u200.dts
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@ -6,6 +6,8 @@
/dts-v1/;
#include "meson-g12a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
/ {
compatible = "amlogic,u200", "amlogic,g12a";
@ -21,9 +23,154 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
};
&cec_AO {
pinctrl-0 = <&cec_ao_a_h_pins>;
pinctrl-names = "default";
status = "disabled";
hdmi-phandle = <&hdmi_tx>;
};
&cecb_AO {
pinctrl-0 = <&cec_ao_b_h_pins>;
pinctrl-names = "default";
status = "okay";
hdmi-phandle = <&hdmi_tx>;
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&vcc_5v>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
vbus-supply = <&usb_pwr_en>;
};
&usb2_phy0 {
phy-supply = <&vcc_5v>;
};
&usb2_phy1 {
phy-supply = <&vcc_5v>;
};

465
arch/arm/dts/meson-g12a.dtsi
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@ -3,9 +3,13 @@
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
compatible = "amlogic,g12a";
@ -55,6 +59,14 @@
};
};
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
clocks = <&clkc CLKID_EFUSE>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -70,6 +82,18 @@
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
};
soc {
@ -85,12 +109,177 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
hdmi_tx: hdmi-tx@0 {
compatible = "amlogic,meson-g12a-dw-hdmi";
reg = <0x0 0x0 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMITX_PHY>,
<&reset RESET_HDMITX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI>,
<&clkc CLKID_HTX_PCLK>,
<&clkc CLKID_VPU_INTR>;
clock-names = "isfr", "iahb", "venci";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;
hdmi_tx_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
/* TMDS Output */
hdmi_tx_tmds_port: port@1 {
reg = <1>;
};
};
periphs: bus@34400 {
compatible = "simple-bus";
reg = <0x0 0x34400 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
periphs_pinctrl: pinctrl@40 {
compatible = "amlogic,meson-g12a-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@40 {
reg = <0x0 0x40 0x0 0x4c>,
<0x0 0xe8 0x0 0x18>,
<0x0 0x120 0x0 0x18>,
<0x0 0x2c0 0x0 0x40>,
<0x0 0x340 0x0 0x1c>;
reg-names = "gpio",
"pull",
"pull-enable",
"mux",
"ds";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 86>;
};
cec_ao_a_h_pins: cec_ao_a_h {
mux {
groups = "cec_ao_a_h";
function = "cec_ao_a_h";
bias-disable;
};
};
cec_ao_b_h_pins: cec_ao_b_h {
mux {
groups = "cec_ao_b_h";
function = "cec_ao_b_h";
bias-disable;
};
};
hdmitx_ddc_pins: hdmitx_ddc {
mux {
groups = "hdmitx_sda",
"hdmitx_sck";
function = "hdmitx";
bias-disable;
};
};
hdmitx_hpd_pins: hdmitx_hpd {
mux {
groups = "hdmitx_hpd_in";
function = "hdmitx";
bias-disable;
};
};
uart_a_pins: uart-a {
mux {
groups = "uart_a_tx",
"uart_a_rx";
function = "uart_a";
bias-disable;
};
};
uart_a_cts_rts_pins: uart-a-cts-rts {
mux {
groups = "uart_a_cts",
"uart_a_rts";
function = "uart_a";
bias-disable;
};
};
uart_b_pins: uart-b {
mux {
groups = "uart_b_tx",
"uart_b_rx";
function = "uart_b";
bias-disable;
};
};
uart_c_pins: uart-c {
mux {
groups = "uart_c_tx",
"uart_c_rx";
function = "uart_c";
bias-disable;
};
};
uart_c_cts_rts_pins: uart-c-cts-rts {
mux {
groups = "uart_c_cts",
"uart_c_rts";
function = "uart_c";
bias-disable;
};
};
};
};
usb2_phy0: phy@36000 {
compatible = "amlogic,g12a-usb2-phy";
reg = <0x0 0x36000 0x0 0x2000>;
clocks = <&xtal>;
clock-names = "xtal";
resets = <&reset RESET_USB_PHY20>;
reset-names = "phy";
#phy-cells = <0>;
};
dmc: bus@38000 {
compatible = "simple-bus";
reg = <0x0 0x38000 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
canvas: video-lut@48 {
compatible = "amlogic,canvas";
reg = <0x0 0x48 0x0 0x14>;
};
};
usb2_phy1: phy@3a000 {
compatible = "amlogic,g12a-usb2-phy";
reg = <0x0 0x3a000 0x0 0x2000>;
clocks = <&xtal>;
clock-names = "xtal";
resets = <&reset RESET_USB_PHY21>;
reset-names = "phy";
#phy-cells = <0>;
};
hiu: bus@3c000 {
@ -113,6 +302,18 @@
};
};
};
usb3_pcie_phy: phy@46000 {
compatible = "amlogic,g12a-usb3-pcie-phy";
reg = <0x0 0x46000 0x0 0x2000>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "ref_clk";
resets = <&reset RESET_PCIE_PHY>;
reset-names = "phy";
assigned-clocks = <&clkc CLKID_PCIE_PLL>;
assigned-clock-rates = <100000000>;
#phy-cells = <1>;
};
};
aobus: bus@ff800000 {
@ -122,6 +323,128 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
rti: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-g12a-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
pwrc_vpu: power-controller-vpu {
compatible = "amlogic,meson-g12a-pwrc-vpu";
#power-domain-cells = <0>;
amlogic,hhi-sysctrl = <&hhi>;
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_BT656>,
<&reset RESET_RDMA>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC>,
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
ao_pinctrl: pinctrl@14 {
compatible = "amlogic,meson-g12a-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x14 0x0 0x8>,
<0x0 0x1c 0x0 0x8>,
<0x0 0x24 0x0 0x14>;
reg-names = "mux",
"ds",
"gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ao_pinctrl 0 0 15>;
};
uart_ao_a_pins: uart-a-ao {
mux {
groups = "uart_ao_a_tx",
"uart_ao_a_rx";
function = "uart_ao_a";
bias-disable;
};
};
uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
mux {
groups = "uart_ao_a_cts",
"uart_ao_a_rts";
function = "uart_ao_a";
bias-disable;
};
};
};
};
cec_AO: cec@100 {
compatible = "amlogic,meson-gx-ao-cec";
reg = <0x0 0x00100 0x0 0x14>;
interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_AO CLKID_AO_CEC>;
clock-names = "core";
status = "disabled";
};
sec_AO: ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
amlogic,has-chip-id;
};
cecb_AO: cec@280 {
compatible = "amlogic,meson-g12a-ao-cec";
reg = <0x0 0x00280 0x0 0x1c>;
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
clock-names = "oscin";
status = "disabled";
};
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
@ -141,6 +464,46 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
saradc: adc@9000 {
compatible = "amlogic,meson-g12a-saradc",
"amlogic,meson-saradc";
reg = <0x0 0x9000 0x0 0x48>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>,
<&clkc_AO CLKID_AO_SAR_ADC>,
<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
clock-names = "clkin", "core", "adc_clk", "adc_sel";
status = "disabled";
};
};
vpu: vpu@ff900000 {
compatible = "amlogic,meson-g12a-vpu";
reg = <0x0 0xff900000 0x0 0x100000>,
<0x0 0xff63c000 0x0 0x1000>;
reg-names = "vpu", "hhi";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
amlogic,canvas = <&canvas>;
power-domains = <&pwrc_vpu>;
/* CVBS VDAC output port */
cvbs_vdac_port: port@0 {
reg = <0>;
};
/* HDMI-TX output port */
hdmi_tx_port: port@1 {
reg = <1>;
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_tx_in>;
};
};
};
gic: interrupt-controller@ffc01000 {
@ -163,10 +526,112 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
reset: reset-controller@1004 {
compatible = "amlogic,meson-g12a-reset",
"amlogic,meson-axg-reset";
reg = <0x0 0x1004 0x0 0x9c>;
#reset-cells = <1>;
};
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
uart_C: serial@22000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x22000 0x0 0x18>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
usb: usb@ffe09000 {
status = "disabled";
compatible = "amlogic,meson-g12a-usb-ctrl";
reg = <0x0 0xffe09000 0x0 0xa0>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>;
resets = <&reset RESET_USB>;
dr_mode = "otg";
phys = <&usb2_phy0>, <&usb2_phy1>,
<&usb3_pcie_phy PHY_TYPE_USB3>;
phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
dwc2: usb@ff400000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "ddr";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@ff500000 {
compatible = "snps,dwc3";
reg = <0x0 0xff500000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_u2_susphy_quirk;
snps,quirk-frame-length-adjustment;
};
};
mali: gpu@ffe40000 {
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
reg = <0x0 0xffe40000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpu", "mmu", "job";
clocks = <&clkc CLKID_MALI>;
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<800000000>,
<0>; /* Do Nothing */
};
};

17
arch/arm/mach-meson/board-gx.c
View File

@ -117,6 +117,11 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
GX_ETH_REG_0_TX_RATIO(4) |
GX_ETH_REG_0_PHY_CLK_EN |
GX_ETH_REG_0_CLK_EN);
/* Reset to external PHY */
if(!IS_ENABLED(CONFIG_MESON_GXBB))
writel(0x2009087f, GX_ETH_REG_3);
break;
case PHY_INTERFACE_MODE_RMII:
@ -124,11 +129,13 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
GX_ETH_REG_0_CLK_EN);
/* Use GXL RMII Internal PHY */
if (IS_ENABLED(CONFIG_MESON_GXL) &&
(flags & MESON_USE_INTERNAL_RMII_PHY)) {
writel(0x10110181, GX_ETH_REG_2);
writel(0xe40908ff, GX_ETH_REG_3);
/* Use GXL RMII Internal PHY (also on GXM) */
if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
writel(0x10110181, GX_ETH_REG_2);
writel(0xe40908ff, GX_ETH_REG_3);
} else
writel(0x2009087f, GX_ETH_REG_3);
}
break;

6
board/amlogic/q200/q200.c
View File

@ -26,12 +26,6 @@ int misc_init_r(void)
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
/* Reset PHY on GPIOZ_14 */
clrbits_le32(GX_GPIO_EN(3), BIT(14));
clrbits_le32(GX_GPIO_OUT(3), BIT(14));
mdelay(10);
setbits_le32(GX_GPIO_OUT(3), BIT(14));
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);

17
configs/u200_defconfig
View File

@ -37,3 +37,20 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB=y
CONFIG_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_PHY=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada

103
drivers/clk/meson/g12a.c
View File

@ -22,6 +22,8 @@ struct meson_clk {
struct regmap *map;
};
static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
ulong rate, ulong current_rate);
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
#define NUM_CLKS 178
@ -36,6 +38,8 @@ static struct meson_gate gates[NUM_CLKS] = {
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
/* Peripheral Gates */
MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
@ -231,6 +235,36 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
return ((parent_rate_mhz * m / n) >> od) * 1000000;
}
static struct parm meson_pcie_pll_parm[3] = {
{HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
{HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
{HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
};
static ulong meson_pcie_pll_get_rate(struct clk *clk)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *pm, *pn, *pod;
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
u16 n, m, od;
uint reg;
pm = &meson_pcie_pll_parm[0];
pn = &meson_pcie_pll_parm[1];
pod = &meson_pcie_pll_parm[2];
regmap_read(priv->map, pn->reg_off, &reg);
n = PARM_GET(pn->width, pn->shift, reg);
regmap_read(priv->map, pm->reg_off, &reg);
m = PARM_GET(pm->width, pm->shift, reg);
regmap_read(priv->map, pod->reg_off, &reg);
od = PARM_GET(pod->width, pod->shift, reg);
return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
}
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
{
ulong rate;
@ -263,6 +297,9 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
case CLKID_CLK81:
rate = meson_clk81_get_rate(clk);
break;
case CLKID_PCIE_PLL:
rate = meson_pcie_pll_get_rate(clk);
break;
default:
if (gates[id].reg != 0) {
/* a clock gate */
@ -281,6 +318,71 @@ static ulong meson_clk_get_rate(struct clk *clk)
return meson_clk_get_rate_by_id(clk, clk->id);
}
static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
{
struct meson_clk *priv = dev_get_priv(clk->dev);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
udelay(20);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
udelay(10);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
udelay(10);
regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
0x1f << 16, 9 << 16);
return 100000000;
}
static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
ulong rate, ulong current_rate)
{
if (current_rate == rate)
return 0;
switch (id) {
/* Fixed clocks */
case CLKID_PCIE_PLL:
return meson_pcie_pll_set_rate(clk, rate);
default:
return -ENOENT;
}
return -EINVAL;
}
static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
{
ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
int ret;
if (IS_ERR_VALUE(current_rate))
return current_rate;
debug("%s: setting rate of %ld from %ld to %ld\n",
__func__, clk->id, current_rate, rate);
ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
if (IS_ERR_VALUE(ret))
return ret;
debug("clock %lu has new rate %lu\n", clk->id,
meson_clk_get_rate_by_id(clk, clk->id));
return 0;
}
static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
@ -298,6 +400,7 @@ static struct clk_ops meson_clk_ops = {
.disable = meson_clk_disable,
.enable = meson_clk_enable,
.get_rate = meson_clk_get_rate,
.set_rate = meson_clk_set_rate,
};
static const struct udevice_id meson_clk_ids[] = {

2
include/dt-bindings/clock/g12a-aoclkc.h
View File

@ -26,7 +26,9 @@
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28

5
include/dt-bindings/clock/g12a-clkc.h
View File

@ -131,5 +131,10 @@
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#endif /* __G12A_CLKC_H */

5
include/dt-bindings/reset/amlogic,meson-g12a-reset.h
View File

@ -51,7 +51,10 @@
#define RESET_SD_EMMC_A 44
#define RESET_SD_EMMC_B 45
#define RESET_SD_EMMC_C 46
/* 47-60 */
/* 47 */
#define RESET_USB_PHY20 48
#define RESET_USB_PHY21 49
/* 50-60 */
#define RESET_AUDIO_CODEC 61
/* 62-63 */
/* RESET2 */