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Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini 2016-04-13 12:53:11 -04:00
commit 541c9be880
46 changed files with 3063 additions and 297 deletions
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3
arch/arm/Kconfig
View File

@ -580,6 +580,7 @@ config ARCH_ZYNQ
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_SPI
@ -592,8 +593,6 @@ config ARCH_ZYNQMP
select ARM64
select DM
select OF_CONTROL
select DM_ETH
select DM_MMC
select DM_SERIAL
config TEGRA

7
arch/arm/dts/Makefile
View File

@ -81,7 +81,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb
zynqmp-ep108.dtb \
zynqmp-zcu102.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

14
arch/arm/dts/zynq-7000.dtsi
View File

@ -96,8 +96,10 @@
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
#interrupt-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
@ -270,6 +272,13 @@
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
@ -297,7 +306,12 @@
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
global_timer: timer@f8f00200 {

38
arch/arm/dts/zynq-microzed.dts
View File

@ -1,7 +1,7 @@
/*
* Xilinx MicroZED board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2013 - 2016 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -15,12 +15,27 @@
aliases {
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&qspi {
@ -32,3 +47,24 @@
u-boot,dm-pre-reloc;
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};

29
arch/arm/dts/zynq-zc702.dts
View File

@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@ -91,6 +91,8 @@
phy-handle = <&ethernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
phy-reset-gpio = <&gpio0 11 0>;
phy-reset-active-low;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
@ -128,6 +130,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "right";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
@ -370,6 +387,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@ -384,11 +406,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

27
arch/arm/dts/zynq-zc706.dts
View File

@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@ -84,6 +84,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "evenly";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
@ -291,6 +306,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@ -305,11 +325,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

44
arch/arm/dts/zynq-zc770-xm010.dts
View File

@ -21,7 +21,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@ -36,27 +36,6 @@
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&qspi {
status = "okay";
};
&can0 {
status = "okay";
};
@ -82,10 +61,31 @@
};
&qspi {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";

3
arch/arm/dts/zynq-zc770-xm011.dts
View File

@ -7,6 +7,7 @@
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
model = "Xilinx Zynq";
@ -18,7 +19,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};

2
arch/arm/dts/zynq-zc770-xm012.dts
View File

@ -20,7 +20,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};

9
arch/arm/dts/zynq-zc770-xm013.dts
View File

@ -16,11 +16,12 @@
ethernet0 = &gem1;
i2c0 = &i2c1;
serial0 = &uart0;
spi0 = &spi0;
spi0 = &qspi;
spi1 = &spi0;
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@ -58,6 +59,10 @@
};
};
&qspi {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <4>;

12
arch/arm/dts/zynq-zed.dts
View File

@ -26,7 +26,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@ -50,6 +50,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@ -60,11 +65,6 @@
status = "okay";
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

14
arch/arm/dts/zynq-zybo.dts
View File

@ -26,13 +26,13 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reset-gpios = <&gpio0 46 1>;
};
};
@ -51,6 +51,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@ -61,11 +66,6 @@
status = "okay";
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

202
arch/arm/dts/zynqmp-clk.dtsi Normal file
View File

@ -0,0 +1,202 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
&amba {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
clk600: clk600 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
dp_aclk: clock0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-accuracy = <100>;
};
dpdma_clk: dpdma_clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
drm_clock: drm_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
clock-accuracy = <0x64>;
};
};
&can0 {
clocks = <&clk100 &clk100>;
};
&can1 {
clocks = <&clk100 &clk100>;
};
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&nand0 {
clocks = <&clk100 &clk100>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem2 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem3 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gpio {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&qspi {
clocks = <&clk300 &clk300>;
};
&sata {
clocks = <&clk250>;
};
&sdhci0 {
clocks = <&clk200 &clk200>;
};
&sdhci1 {
clocks = <&clk200 &clk200>;
};
&spi0 {
clocks = <&clk200 &clk200>;
};
&spi1 {
clocks = <&clk200 &clk200>;
};
&uart0 {
clocks = <&clk100 &clk100>;
};
&uart1 {
clocks = <&clk100 &clk100>;
};
&usb0 {
clocks = <&clk250>, <&clk250>;
};
&usb1 {
clocks = <&clk250>, <&clk250>;
};
&xilinx_drm {
clocks = <&drm_clock>;
};
&xlnx_dp {
clocks = <&dp_aclk>, <&dp_aud_clk>;
};
&xlnx_dpdma {
clocks = <&dpdma_clk>;
};
&xlnx_dp_snd_codec0 {
clocks = <&dp_aud_clk>;
};

4
arch/arm/dts/zynqmp-ep108-clk.dtsi
View File

@ -62,6 +62,10 @@
clocks = <&i2c_clk>;
};
&nand0 {
clocks = <&misc_clk &misc_clk>;
};
&qspi {
clocks = <&misc_clk &misc_clk>;
};

61
arch/arm/dts/zynqmp-ep108.dts
View File

@ -10,17 +10,21 @@
/dts-v1/;
/include/ "zynqmp.dtsi"
/include/ "zynqmp-ep108-clk.dtsi"
#include "zynqmp.dtsi"
#include "zynqmp-ep108-clk.dtsi"
/ {
model = "ZynqMP EP108";
aliases {
mmc0 = &sdhci0;
mmc1 = &sdhci1;
serial0 = &uart0;
spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
@ -29,7 +33,7 @@
memory {
device_type = "memory";
reg = <0x0 0x0 0x40000000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
};
@ -69,10 +73,41 @@
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <1>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "n25q512a11";
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
@ -101,10 +136,20 @@
&sata {
status = "okay";
ceva,broken-gen2;
/* SATA Phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
};
&sdhci0 {
status = "okay";
bus-width = <8>;
};
&sdhci1 {
@ -151,12 +196,20 @@
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
&usb1 {
status = "okay";
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "high-speed";
};

211
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts Normal file
View File

@ -0,0 +1,211 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
compatible = "at,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
/* eMMC */
&sdhci0 {
status = "okay";
bus-width = <8>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
};
&uart0 {
status = "okay";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&xilinx_drm {
status = "okay";
};
&xlnx_dp {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

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/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &gem2;
gpio0 = &gpio;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem2 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* IRQ not connected */
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <2>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
partition@6 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x1 0x0 0x400000>;
};
partition@7 { /* for testing purpose */
label = "nand1-linux";
reg = <0x1 0x400000 0x1400000>;
};
partition@8 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x1 0x1800000 0x400000>;
};
partition@9 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x1 0x1C00000 0x1400000>;
};
partition@10 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x1 0x3000000 0x400000>;
};
partition@11 { /* for testing purpose */
label = "nand1-misc";
reg = <0x1 0x3400000 0xFCC00000>;
};
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <1>;
spi0_flash0: spi0_flash0@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi0_flash0@00000000 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
};
};
&spi1 {
status = "okay";
num-cs = <1>;
spi1_flash0: spi1_flash0@0 {
compatible = "mtd_dataflash";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi1_flash0@00000000 {
label = "spi1_flash0";
reg = <0x0 0x84000>;
};
};
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

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/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem1;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem1 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
/* FIXME: Add device */
&i2c0 {
status = "okay";
};
/* FIXME: Add device */
&i2c1 {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

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/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
* (C) Copyright 2016, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "zynqmp-zcu102.dts"
/ {
model = "ZynqMP ZCU102 RevB";
};
&gem3 {
phy-handle = <&phyc>;
phyc: phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
/* Cleanup from RevA */
/delete-node/ phy@21;
};
/* Different qspi 512Mbit version */
/* Fix collision with u61 */
&i2c0 {
i2cswitch@75 {
i2c@2 {
max15303@1b { /* u8 */
compatible = "max15303";
reg = <0x1b>;
};
/delete-node/ max15303@20;
};
};
};

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/*
* dts file for Xilinx ZynqMP ZCU102
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP ZCU102 RevA";
compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can1 {
status = "okay";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u97: gpio@20 {
/*
* Enable all GTs to out from U-Boot
* i2c mw 20 6 0 - setup IO to output
* i2c mw 20 2 ef - setup output values on pins 0-7
* i2c mw 20 3 ff - setup output values on pins 10-17
*/
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - PS_GTR_LAN_SEL0
* 1 - PS_GTR_LAN_SEL1
* 2 - PS_GTR_LAN_SEL2
* 3 - PS_GTR_LAN_SEL3
* 4 - PCI_CLK_DIR_SEL
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 7, 10 - 17 - not connected
*/
gtr_sel0 {
gpio-hog;
gpios = <0 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr_sel1 {
gpio-hog;
gpios = <1 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel1";
};
gtr_sel2 {
gpio-hog;
gpios = <2 0>;
output-high; /* PCIE = 0, USB0 = 1 */
line-name = "sel2";
};
gtr_sel3 {
gpio-hog;
gpios = <3 0>;
output-high; /* PCIE = 0, SATA = 1 */
line-name = "sel3";
};
};
tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - VCCPSPLL_EN
* 1 - MGTRAVCC_EN
* 2 - MGTRAVTT_EN
* 3 - VCCPSDDRPLL_EN
* 4 - MIO26_PMU_INPUT_LS
* 5 - PL_PMBUS_ALERT
* 6 - PS_PMBUS_ALERT
* 7 - MAXIM_PMBUS_ALERT
* 10 - PL_DDR4_VTERM_EN
* 11 - PL_DDR4_VPP_2V5_EN
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
* 13 - PS_DIMM_SUSPEND_EN
* 14 - PS_DDR4_VTERM_EN
* 15 - PS_DDR4_VPP_2V5_EN
* 16 - 17 - not connected
*/
};
i2cswitch@75 { /* u60 */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
ina226@40 { /* u76 */
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <5000>;
};
ina226@41 { /* u77 */
compatible = "ti,ina226";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u78 */
compatible = "ti,ina226";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u87 */
compatible = "ti,ina226";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u85 */
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u86 */
compatible = "ti,ina226";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u93 */
compatible = "ti,ina226";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u88 */
compatible = "ti,ina226";
reg = <0x47>;
shunt-resistor = <5000>;
};
ina226@4a { /* u15 */
compatible = "ti,ina226";
reg = <0x4a>;
shunt-resistor = <5000>;
};
ina226@4b { /* u92 */
compatible = "ti,ina226";
reg = <0x4b>;
shunt-resistor = <5000>;
};
};
i2c@1 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* PL_PMBUS */
ina226@40 { /* u79 */
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina226@41 { /* u81 */
compatible = "ti,ina226";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u80 */
compatible = "ti,ina226";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u84 */
compatible = "ti,ina226";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u16 */
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u65 */
compatible = "ti,ina226";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u74 */
compatible = "ti,ina226";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u75 */
compatible = "ti,ina226";
reg = <0x47>;
shunt-resistor = <5000>;
};
};
i2c@2 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* MAXIM_PMBUS - 00 */
max15301@a { /* u46 */
compatible = "max15301";
reg = <0xa>;
};
max15303@b { /* u4 */
compatible = "max15303";
reg = <0xb>;
};
max15303@10 { /* u13 */
compatible = "max15303";
reg = <0x10>;
};
max15301@13 { /* u47 */
compatible = "max15301";
reg = <0x13>;
};
max15303@14 { /* u7 */
compatible = "max15303";
reg = <0x14>;
};
max15303@15 { /* u6 */
compatible = "max15303";
reg = <0x15>;
};
max15303@16 { /* u10 */
compatible = "max15303";
reg = <0x16>;
};
max15303@17 { /* u9 */
compatible = "max15303";
reg = <0x17>;
};
max15301@18 { /* u63 */
compatible = "max15301";
reg = <0x18>;
};
max15303@1a { /* u49 */
compatible = "max15303";
reg = <0x1a>;
};
max15303@1d { /* u18 */
compatible = "max15303";
reg = <0x1d>;
};
max15303@20 { /* u8 */
compatible = "max15303";
status = "disabled"; /* unreachable */
reg = <0x20>;
};
/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
*/
max20751@72 { /* u95 FIXME - not detected */
compatible = "max20751";
reg = <0x72>;
};
max20751@73 { /* u96 FIXME - not detected */
compatible = "max20751";
reg = <0x73>;
};
};
/* Bus 3 is not connected */
};
/* FIXME PL connection - u55 , PMOD - j160 */
/* FIXME MSP430F - u41 - not detected */
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
/* FIXME PL i2c via PCA9306 - u45 */
/* FIXME MSP430 - u41 - not detected */
i2cswitch@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 { /* i2c mw 74 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* IIC_EEPROM 1kB memory which uses 256B blocks
* where every block has different address.
* 0 - 256B address 0x54
* 256B - 512B address 0x55
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
eeprom@54 { /* u23 */
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@1 { /* i2c mw 74 0 2 */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
si5341: clock-generator1@36 { /* SI5341 - u69 */
compatible = "si5341";
reg = <0x36>;
};
};
i2c@2 { /* i2c mw 74 0 4 */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
si570_1: clock-generator2@5d { /* USER SI570 - u42 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
};
};
i2c@3 { /* i2c mw 74 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@4 { /* i2c mw 74 0 10 */
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator4@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
};
};
/* 5 - 7 unconnected */
};
i2cswitch@75 {
compatible = "nxp,pca9548"; /* u135 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* HPC0_IIC */
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* HPC1_IIC */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* SYSMON */
};
i2c@3 { /* i2c mw 75 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
dev@19 { /* u-boot detection */
compatible = "xxx";
reg = <0x19>;
};
dev@30 { /* u-boot detection */
compatible = "xxx";
reg = <0x30>;
};
dev@35 { /* u-boot detection */
compatible = "xxx";
reg = <0x35>;
};
dev@36 { /* u-boot detection */
compatible = "xxx";
reg = <0x36>;
};
dev@51 { /* u-boot detection - maybe SPD */
compatible = "xxx";
reg = <0x51>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* SEP 3 */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* SEP 2 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* SEP 1 */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
/* SEP 0 */
};
};
};
&pcie {
/* status = "okay"; */
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "m25p80"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
};
&xilinx_drm {
status = "okay";
clocks = <&si570_1>;
};
&xlnx_dp {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

382
arch/arm/dts/zynqmp.dtsi
View File

@ -10,7 +10,7 @@
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <1>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
@ -45,8 +45,179 @@
};
};
power-domains {
compatible = "xlnx,zynqmp-genpd";
pd_usb0: pd-usb0 {
#power-domain-cells = <0x0>;
pd-id = <0x16>;
};
pd_usb1: pd-usb1 {
#power-domain-cells = <0x0>;
pd-id = <0x17>;
};
pd_sata: pd-sata {
#power-domain-cells = <0x0>;
pd-id = <0x1c>;
};
pd_spi0: pd-spi0 {
#power-domain-cells = <0x0>;
pd-id = <0x23>;
};
pd_spi1: pd-spi1 {
#power-domain-cells = <0x0>;
pd-id = <0x24>;
};
pd_uart0: pd-uart0 {
#power-domain-cells = <0x0>;
pd-id = <0x21>;
};
pd_uart1: pd-uart1 {
#power-domain-cells = <0x0>;
pd-id = <0x22>;
};
pd_eth0: pd-eth0 {
#power-domain-cells = <0x0>;
pd-id = <0x1d>;
};
pd_eth1: pd-eth1 {
#power-domain-cells = <0x0>;
pd-id = <0x1e>;
};
pd_eth2: pd-eth2 {
#power-domain-cells = <0x0>;
pd-id = <0x1f>;
};
pd_eth3: pd-eth3 {
#power-domain-cells = <0x0>;
pd-id = <0x20>;
};
pd_i2c0: pd-i2c0 {
#power-domain-cells = <0x0>;
pd-id = <0x25>;
};
pd_i2c1: pd-i2c1 {
#power-domain-cells = <0x0>;
pd-id = <0x26>;
};
pd_dp: pd-dp {
/* fixme: what to attach to */
#power-domain-cells = <0x0>;
pd-id = <0x29>;
};
pd_gdma: pd-gdma {
#power-domain-cells = <0x0>;
pd-id = <0x2a>;
};
pd_adma: pd-adma {
#power-domain-cells = <0x0>;
pd-id = <0x2b>;
};
pd_ttc0: pd-ttc0 {
#power-domain-cells = <0x0>;
pd-id = <0x18>;
};
pd_ttc1: pd-ttc1 {
#power-domain-cells = <0x0>;
pd-id = <0x19>;
};
pd_ttc2: pd-ttc2 {
#power-domain-cells = <0x0>;
pd-id = <0x1a>;
};
pd_ttc3: pd-ttc3 {
#power-domain-cells = <0x0>;
pd-id = <0x1b>;
};
pd_sd0: pd-sd0 {
#power-domain-cells = <0x0>;
pd-id = <0x27>;
};
pd_sd1: pd-sd1 {
#power-domain-cells = <0x0>;
pd-id = <0x28>;
};
pd_nand: pd-nand {
#power-domain-cells = <0x0>;
pd-id = <0x2c>;
};
pd_qspi: pd-qspi {
#power-domain-cells = <0x0>;
pd-id = <0x2d>;
};
pd_gpio: pd-gpio {
#power-domain-cells = <0x0>;
pd-id = <0x2e>;
};
pd_can0: pd-can0 {
#power-domain-cells = <0x0>;
pd-id = <0x2f>;
};
pd_can1: pd-can1 {
#power-domain-cells = <0x0>;
pd-id = <0x30>;
};
pd_ddr: pd-ddr {
#power-domain-cells = <0x0>;
pd-id = <0x37>;
};
pd_apll: pd-apll {
#power-domain-cells = <0x0>;
pd-id = <0x32>;
};
pd_vpll: pd-vpll {
#power-domain-cells = <0x0>;
pd-id = <0x33>;
};
pd_dpll: pd-dpll {
#power-domain-cells = <0x0>;
pd-id = <0x34>;
};
pd_rpll: pd-rpll {
#power-domain-cells = <0x0>;
pd-id = <0x35>;
};
pd_iopll: pd-iopll {
#power-domain-cells = <0x0>;
pd-id = <0x36>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <0 143 4>,
<0 144 4>,
<0 145 4>,
@ -76,7 +247,7 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
@ -95,7 +266,7 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
ranges = <0 0 0 0 0xffffffff>;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
@ -106,6 +277,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <&pd_can0>;
};
can1: can@ff070000 {
@ -117,6 +289,26 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <&pd_can1>;
};
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
reg = <0x0 0xfd6e0000 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <&gic>;
interrupts = <0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>;
};
};
/* GDMA */
@ -126,8 +318,10 @@
reg = <0x0 0xfd500000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <0>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan2: dma@fd510000 {
@ -136,8 +330,10 @@
reg = <0x0 0xfd510000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <1>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan3: dma@fd520000 {
@ -146,8 +342,10 @@
reg = <0x0 0xfd520000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <2>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan4: dma@fd530000 {
@ -156,8 +354,10 @@
reg = <0x0 0xfd530000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <3>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan5: dma@fd540000 {
@ -166,8 +366,10 @@
reg = <0x0 0xfd540000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <4>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan6: dma@fd550000 {
@ -176,8 +378,10 @@
reg = <0x0 0xfd550000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <5>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan7: dma@fd560000 {
@ -186,8 +390,10 @@
reg = <0x0 0xfd560000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <6>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan8: dma@fd570000 {
@ -196,8 +402,10 @@
reg = <0x0 0xfd570000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <7>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
gpu: gpu@fd4b0000 {
@ -218,6 +426,7 @@
interrupts = <0 77 4>;
xlnx,id = <0>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan2: dma@ffa90000 {
@ -228,6 +437,7 @@
interrupts = <0 78 4>;
xlnx,id = <1>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan3: dma@ffaa0000 {
@ -238,6 +448,7 @@
interrupts = <0 79 4>;
xlnx,id = <2>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan4: dma@ffab0000 {
@ -248,6 +459,7 @@
interrupts = <0 80 4>;
xlnx,id = <3>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan5: dma@ffac0000 {
@ -258,6 +470,7 @@
interrupts = <0 81 4>;
xlnx,id = <4>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan6: dma@ffad0000 {
@ -268,6 +481,7 @@
interrupts = <0 82 4>;
xlnx,id = <5>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan7: dma@ffae0000 {
@ -278,6 +492,7 @@
interrupts = <0 83 4>;
xlnx,id = <6>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan8: dma@ffaf0000 {
@ -288,6 +503,14 @@
interrupts = <0 84 4>;
xlnx,id = <7>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
mc: memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
nand0: nand@ff100000 {
@ -299,10 +522,11 @@
interrupts = <0 14 4>;
#address-cells = <2>;
#size-cells = <1>;
power-domains = <&pd_nand>;
};
gem0: ethernet@ff0b0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
@ -310,12 +534,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth0>;
};
gem1: ethernet@ff0c0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
@ -323,12 +547,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth1>;
};
gem2: ethernet@ff0d0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
@ -336,12 +560,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth2>;
};
gem3: ethernet@ff0e0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
@ -349,17 +573,20 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth3>;
};
gpio: gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
reg = <0x0 0xff0a0000 0x1000>;
power-domains = <&pd_gpio>;
};
i2c0: i2c@ff020000 {
@ -370,6 +597,7 @@
reg = <0x0 0xff020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c0>;
};
i2c1: i2c@ff030000 {
@ -380,6 +608,7 @@
reg = <0x0 0xff030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c1>;
};
pcie: pcie@fd0e0000 {
@ -390,16 +619,26 @@
#interrupt-cells = <1>;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = < 0 118 4>,
< 0 116 4>,
< 0 115 4>, /* MSI_1 [63...32] */
< 0 114 4 >; /* MSI_0 [31...0] */
interrupts = <0 118 4>,
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
interrupt-names = "misc", "intx", "msi_1", "msi_0";
reg = <0x0 0xfd0e0000 0x1000>,
<0x0 0xfd480000 0x1000>,
<0x0 0xe0000000 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
qspi: spi@ff0f0000 {
@ -409,9 +648,11 @@
interrupts = <0 15 4>;
interrupt-parent = <&gic>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
reg = <0x0 0xff0f0000 0x1000>,
<0x0 0xc0000000 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_qspi>;
};
rtc: rtc@ffa60000 {
@ -429,6 +670,7 @@
reg = <0x0 0xfd0c0000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
};
sdhci0: sdhci@ff160000 {
@ -438,6 +680,8 @@
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
broken-tuning;
power-domains = <&pd_sd0>;
};
sdhci1: sdhci@ff170000 {
@ -447,6 +691,8 @@
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
broken-tuning;
power-domains = <&pd_sd1>;
};
smmu: smmu@fd800000 {
@ -454,11 +700,15 @@
reg = <0x0 0xfd800000 0x20000>;
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
interrupts = <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
mmu-masters = < &gem0 0x874
&gem1 0x875
&gem2 0x876
&gem3 0x877 >;
};
spi0: spi@ff040000 {
@ -470,6 +720,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_spi0>;
};
spi1: spi@ff050000 {
@ -481,6 +732,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_spi1>;
};
ttc0: timer@ff110000 {
@ -490,6 +742,7 @@
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc0>;
};
ttc1: timer@ff120000 {
@ -499,6 +752,7 @@
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc1>;
};
ttc2: timer@ff130000 {
@ -508,6 +762,7 @@
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc2>;
};
ttc3: timer@ff140000 {
@ -517,42 +772,69 @@
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc3>;
};
uart0: serial@ff000000 {
compatible = "cdns,uart-r1p12";
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart0>;
};
uart1: serial@ff010000 {
compatible = "cdns,uart-r1p12";
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart1>;
};
usb0: usb@fe200000 {
compatible = "snps,dwc3";
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
power-domains = <&pd_usb0>;
ranges;
dwc3_0: dwc3@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
snps,refclk_fladj;
};
};
usb1: usb@fe300000 {
compatible = "snps,dwc3";
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
power-domains = <&pd_usb1>;
ranges;
dwc3_1: dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
snps,refclk_fladj;
};
};
watchdog0: watchdog@fd4d0000 {
@ -583,10 +865,11 @@
};
};
xlnx_dp: dp@43c00000 {
xlnx_dp: dp@fd4a0000 {
compatible = "xlnx,v-dp";
status = "disabled";
reg = <0x0 0xfd4a0000 0x1000>;
reg = <0x0 0xfd4a0000 0x1000>,
<0x0 0xfd400000 0x20000>;
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
@ -599,6 +882,7 @@
xlnx,bpc = <8>;
xlnx,audio-chan = <2>;
xlnx,dp-sub = <&xlnx_dp_sub>;
xlnx,max-pclock-frequency = <300000>;
};
xlnx_dp_snd_card: dp_snd_card {
@ -628,12 +912,16 @@
dma-names = "tx";
};
xlnx_dp_sub: dp_sub@43c0a000 {
xlnx_dp_sub: dp_sub@fd4aa000 {
compatible = "xlnx,dp-sub";
status = "disabled";
reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
reg = <0x0 0xfd4aa000 0x1000>,
<0x0 0xfd4ab000 0x1000>,
<0x0 0xfd4ac000 0x1000>;
reg-names = "blend", "av_buf", "aud";
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
};
xlnx_dpdma: dma@fd4c0000 {
@ -645,22 +933,22 @@
clock-names = "axi_clk";
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel@43c10000 {
dma-video0channel@fd4c0000 {
compatible = "xlnx,video0";
};
dma-video1channel@43c10000 {
dma-video1channel@fd4c0000 {
compatible = "xlnx,video1";
};
dma-video2channel@43c10000 {
dma-video2channel@fd4c0000 {
compatible = "xlnx,video2";
};
dma-graphicschannel@43c10000 {
dma-graphicschannel@fd4c0000 {
compatible = "xlnx,graphics";
};
dma-audio0channel@43c10000 {
dma-audio0channel@fd4c0000 {
compatible = "xlnx,audio0";
};
dma-audio1channel@43c10000 {
dma-audio1channel@fd4c0000 {
compatible = "xlnx,audio1";
};
};

63
arch/arm/mach-zynq/include/mach/gpio.h
View File

@ -8,67 +8,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK 4
#define ZYNQ_GPIO_BANK0_NGPIO 32
#define ZYNQ_GPIO_BANK1_NGPIO 22
#define ZYNQ_GPIO_BANK2_NGPIO 32
#define ZYNQ_GPIO_BANK3_NGPIO 32
#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
ZYNQ_GPIO_BANK1_NGPIO + \
ZYNQ_GPIO_BANK2_NGPIO + \
ZYNQ_GPIO_BANK3_NGPIO)
#define ZYNQ_GPIO_BANK0_PIN_MIN 0
#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
ZYNQ_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
ZYNQ_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
ZYNQ_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
ZYNQ_GPIO_BANK3_NGPIO - 1)
/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
#endif /* _ZYNQ_GPIO_H */

134
board/xilinx/zynq/board.c
View File

@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
return 0;
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
/*
* fdt_get_reg - Fill buffer by information from DT
*/
static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
const u32 *cell, int n)
{
int i = 0, b, banks;
int parent_offset = fdt_parent_offset(fdt, nodeoffset);
int address_cells = fdt_address_cells(fdt, parent_offset);
int size_cells = fdt_size_cells(fdt, parent_offset);
char *p = buf;
u64 val;
u64 vals;
debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
__func__, address_cells, size_cells, buf, cell);
/* Check memory bank setup */
banks = n % (address_cells + size_cells);
if (banks)
panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
n, address_cells, size_cells);
banks = n / (address_cells + size_cells);
for (b = 0; b < banks; b++) {
debug("%s: Bank #%d:\n", __func__, b);
if (address_cells == 2) {
val = cell[i + 1];
val <<= 32;
val |= cell[i];
val = fdt64_to_cpu(val);
debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
__func__, val, p, &cell[i]);
*(phys_addr_t *)p = val;
} else {
debug("%s: addr32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_addr_t);
i += address_cells;
debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
sizeof(phys_addr_t));
if (size_cells == 2) {
vals = cell[i + 1];
vals <<= 32;
vals |= cell[i];
vals = fdt64_to_cpu(vals);
debug("%s: size64=%llx, ptr=%p, cell=%p\n",
__func__, vals, p, &cell[i]);
*(phys_size_t *)p = vals;
} else {
debug("%s: size32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_size_t);
i += size_cells;
debug("%s: ps=%p, i=%x, size=%zu\n",
__func__, p, i, sizeof(phys_size_t));
}
/* Return the first address size */
return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
}
#define FDT_REG_SIZE sizeof(u32)
/* Temp location for sharing data for storing */
/* Up to 64-bit address + 64-bit size */
static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
void dram_init_banksize(void)
{
int bank;
memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
debug("Bank #%d: start %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].start);
debug("Bank #%d: size %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].size);
}
}
int dram_init(void)
{
int node;
fdt_addr_t addr;
fdt_size_t size;
int node, len;
const void *blob = gd->fdt_blob;
const u32 *cell;
node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
"memory", 7);
if (node == -FDT_ERR_NOTFOUND) {
debug("ZYNQ DRAM: Can't get memory node\n");
memset(&tmp, 0, sizeof(tmp));
/* find or create "/memory" node. */
node = fdt_subnode_offset(blob, 0, "memory");
if (node < 0) {
printf("%s: Can't get memory node\n", __func__);
return node;
}
/* Get pointer to cells and lenght of it */
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell) {
printf("%s: Can't get reg property\n", __func__);
return -1;
}
addr = fdtdec_get_addr_size(blob, node, "reg", &size);
if (addr == FDT_ADDR_T_NONE || size == 0) {
debug("ZYNQ DRAM: Can't get base address or size\n");
return -1;
}
gd->ram_size = size;
gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
zynq_ddrc_init();
return 0;
}
#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
zynq_ddrc_init();
return 0;
}
#endif

7
board/xilinx/zynqmp/zynqmp.c
View File

@ -6,7 +6,6 @@
*/
#include <common.h>
#include <netdev.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
@ -63,8 +62,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
int address_cells = fdt_address_cells(fdt, parent_offset);
int size_cells = fdt_size_cells(fdt, parent_offset);
char *p = buf;
phys_addr_t val;
phys_size_t vals;
u64 val;
u64 vals;
debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
__func__, address_cells, size_cells, buf, cell);
@ -166,7 +165,7 @@ int dram_init(void)
gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
return 0;
}

8
configs/xilinx_zynqmp_ep_defconfig
View File

@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
@ -15,7 +18,9 @@ CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
@ -26,8 +31,11 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_NAND_ARASAN=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_GADGET=y

37
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig Normal file
View File

@ -0,0 +1,37 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

35
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig Normal file
View File

@ -0,0 +1,35 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

24
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig Normal file
View File

@ -0,0 +1,24 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_DM_ETH=y

34
configs/xilinx_zynqmp_zcu102_defconfig Normal file
View File

@ -0,0 +1,34 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

34
configs/xilinx_zynqmp_zcu102_revB_defconfig Normal file
View File

@ -0,0 +1,34 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DM_GPIO=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

4
configs/zynq_microzed_defconfig
View File

@ -21,3 +21,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y

20
doc/device-tree-bindings/i2c/i2c-cdns.txt Normal file
View File

@ -0,0 +1,20 @@
Cadence I2C controller Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10".
- reg : Physical base address and size of I2C registers map.
- interrupts : Property with a value describing the interrupt
number.
- interrupt-parent : Must be core interrupt controller
- clocks : Clock phandles (see clock bindings for details).
Example:
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
reg = <0xe0004000 0x1000>;
clocks = <&clkc 38>;
interrupts = <0 25 4>;
interrupt-parent = <&intc>;
status = "disabled";
};

7
drivers/gpio/Kconfig
View File

@ -136,4 +136,11 @@ config MVEBU_GPIO
help
Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
config ZYNQ_GPIO
bool "Zynq GPIO driver"
depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
default y
help
Supports GPIO access on Zynq SoC.
endmenu

4
drivers/gpio/pca953x.c
View File

@ -217,7 +217,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* All commands but "device" require 'maxargs' arguments */
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == PCA953X_CMD_DEVICE) &&
(((long)c->cmd == PCA953X_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
return CMD_RET_USAGE;
}
@ -230,7 +230,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (argc > 3)
ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1;
switch ((int)c->cmd) {
switch ((long)c->cmd) {
#ifdef CONFIG_CMD_PCA953X_INFO
case PCA953X_CMD_INFO:
ret = pca953x_info(chip);

338
drivers/gpio/zynq_gpio.c
View File

@ -13,6 +13,141 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <dm.h>
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK 4
#define ZYNQ_GPIO_BANK0_NGPIO 32
#define ZYNQ_GPIO_BANK1_NGPIO 22
#define ZYNQ_GPIO_BANK2_NGPIO 32
#define ZYNQ_GPIO_BANK3_NGPIO 32
#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
ZYNQ_GPIO_BANK1_NGPIO + \
ZYNQ_GPIO_BANK2_NGPIO + \
ZYNQ_GPIO_BANK3_NGPIO)
#define ZYNQMP_GPIO_MAX_BANK 6
#define ZYNQMP_GPIO_BANK0_NGPIO 26
#define ZYNQMP_GPIO_BANK1_NGPIO 26
#define ZYNQMP_GPIO_BANK2_NGPIO 26
#define ZYNQMP_GPIO_BANK3_NGPIO 32
#define ZYNQMP_GPIO_BANK4_NGPIO 32
#define ZYNQMP_GPIO_BANK5_NGPIO 32
#define ZYNQMP_GPIO_NR_GPIOS 174
#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
struct zynq_gpio_privdata {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
/**
* struct zynq_platform_data - zynq gpio platform data structure
* @label: string to store in gpio->label
* @ngpio: max number of gpio pins
* @max_bank: maximum number of gpio banks
* @bank_min: this array represents bank's min pin
* @bank_max: this array represents bank's max pin
*/
struct zynq_platform_data {
const char *label;
u16 ngpio;
int max_bank;
int bank_min[ZYNQMP_GPIO_MAX_BANK];
int bank_max[ZYNQMP_GPIO_MAX_BANK];
};
static const struct zynq_platform_data zynqmp_gpio_def = {
.label = "zynqmp_gpio",
.ngpio = ZYNQMP_GPIO_NR_GPIOS,
.max_bank = ZYNQMP_GPIO_MAX_BANK,
.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
};
static const struct zynq_platform_data zynq_gpio_def = {
.label = "zynq_gpio",
.ngpio = ZYNQ_GPIO_NR_GPIOS,
.max_bank = ZYNQ_GPIO_MAX_BANK,
.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
};
/**
* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
@ -27,88 +162,71 @@
*/
static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
unsigned int *bank_num,
unsigned int *bank_pin_num)
unsigned int *bank_pin_num,
struct udevice *dev)
{
switch (pin_num) {
case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
*bank_num = 0;
*bank_pin_num = pin_num;
break;
case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
*bank_num = 1;
*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
break;
case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
*bank_num = 2;
*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
break;
case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
*bank_num = 3;
*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
break;
default:
printf("invalid GPIO pin number: %u\n", pin_num);
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
int bank;
for (bank = 0; bank < priv->p_data->max_bank; bank++) {
if ((pin_num >= priv->p_data->bank_min[bank]) &&
(pin_num <= priv->p_data->bank_max[bank])) {
*bank_num = bank;
*bank_pin_num = pin_num -
priv->p_data->bank_min[bank];
return;
}
}
if (bank >= priv->p_data->max_bank) {
printf("Inavlid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
break;
}
}
int gpio_is_valid(unsigned gpio)
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
return (gpio >= 0) && (gpio < priv->p_data->ngpio);
}
static int check_gpio(unsigned gpio)
static int check_gpio(unsigned gpio, struct udevice *dev)
{
if (!gpio_is_valid(gpio)) {
if (!gpio_is_valid(gpio, dev)) {
printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
return -1;
}
return 0;
}
/**
* gpio_get_value - Get the state of the specified pin of GPIO device
* @gpio: gpio pin number within the device
*
* This function reads the state of the specified pin of the GPIO device.
*
* Return: 0 if the pin is low, 1 if pin is high.
*/
int gpio_get_value(unsigned gpio)
static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
{
u32 data;
unsigned int bank_num, bank_pin_num;
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
if (check_gpio(gpio) < 0)
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
data = readl(ZYNQ_GPIO_BASE_ADDRESS +
data = readl(priv->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
}
/**
* gpio_set_value - Modify the value of the pin with specified value
* @gpio: gpio pin number within the device
* @value: value used to modify the value of the specified pin
*
* This function calculates the register offset (i.e to lower 16 bits or
* upper 16 bits) based on the given pin number and sets the value of a
* gpio pin to the specified value. The value is either 0 or non-zero.
*/
int gpio_set_value(unsigned gpio, int value)
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
if (check_gpio(gpio) < 0)
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
/* only 16 data bits in bit maskable reg */
@ -126,95 +244,127 @@ int gpio_set_value(unsigned gpio, int value)
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset);
writel(value, priv->base + reg_offset);
return 0;
}
/**
* gpio_direction_input - Set the direction of the specified GPIO pin as input
* @gpio: gpio pin number within the device
*
* This function uses the read-modify-write sequence to set the direction of
* the gpio pin as input.
*
* Return: -1 if invalid gpio specified, 0 if successul
*/
int gpio_direction_input(unsigned gpio)
static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
if (check_gpio(gpio) < 0)
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
return -1;
/* clear the bit in direction mode reg to set the pin as input */
reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
/**
* gpio_direction_output - Set the direction of the specified GPIO pin as output
* @gpio: gpio pin number within the device
* @value: value to be written to specified pin
*
* This function sets the direction of specified GPIO pin as output, configures
* the Output Enable register for the pin and uses zynq_gpio_set to set
* the value of the pin to the value specified.
*
* Return: 0 always
*/
int gpio_direction_output(unsigned gpio, int value)
static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
int value)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
if (check_gpio(gpio) < 0)
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
gpio_set_value(gpio, value);
return 0;
}
/**
* Request a gpio before using it.
*
* NOTE: Argument 'label' is unused.
*/
int gpio_request(unsigned gpio, const char *label)
static const struct dm_gpio_ops gpio_zynq_ops = {
.direction_input = zynq_gpio_direction_input,
.direction_output = zynq_gpio_direction_output,
.get_value = zynq_gpio_get_value,
.set_value = zynq_gpio_set_value,
};
static const struct udevice_id zynq_gpio_ids[] = {
{ .compatible = "xlnx,zynq-gpio-1.0",
.data = (ulong)&zynq_gpio_def},
{ .compatible = "xlnx,zynqmp-gpio-1.0",
.data = (ulong)&zynqmp_gpio_def},
{ }
};
static void zynq_gpio_getplat_data(struct udevice *dev)
{
if (check_gpio(gpio) < 0)
return -1;
const struct udevice_id *of_match = zynq_gpio_ids;
int ret;
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
while (of_match->compatible) {
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
of_match->compatible);
if (ret >= 0) {
priv->p_data =
(struct zynq_platform_data *)of_match->data;
break;
} else {
of_match++;
continue;
}
}
if (!priv->p_data)
printf("No Platform data found\n");
}
static int zynq_gpio_probe(struct udevice *dev)
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
zynq_gpio_getplat_data(dev);
if (priv->p_data)
uc_priv->gpio_count = priv->p_data->ngpio;
return 0;
}
/**
* Reset and free the gpio after using it.
*/
int gpio_free(unsigned gpio)
static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
priv->base = dev_get_addr(dev);
return 0;
}
U_BOOT_DRIVER(gpio_zynq) = {
.name = "gpio_zynq",
.id = UCLASS_GPIO,
.ops = &gpio_zynq_ops,
.of_match = zynq_gpio_ids,
.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
.probe = zynq_gpio_probe,
.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
};

7
drivers/i2c/Kconfig
View File

@ -58,6 +58,13 @@ config DM_I2C_GPIO
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
config SYS_I2C_CADENCE
tristate "Cadence I2C Controller"
depends on DM_I2C && (ARCH_ZYNQ || ARM64)
help
Say yes here to select Cadence I2C Host Controller. This controller is
e.g. used by Xilinx Zynq.
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C

1
drivers/i2c/Makefile
View File

@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o

335
drivers/i2c/i2c-cdns.c Normal file
View File

@ -0,0 +1,335 @@
/*
* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
*
* This file is based on: drivers/i2c/zynq_i2c.c,
* with added driver-model support and code cleanup.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <linux/io.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
/* i2c register set */
struct cdns_i2c_regs {
u32 control;
u32 status;
u32 address;
u32 data;
u32 interrupt_status;
u32 transfer_size;
u32 slave_mon_pause;
u32 time_out;
u32 interrupt_mask;
u32 interrupt_enable;
u32 interrupt_disable;
};
/* Control register fields */
#define CDNS_I2C_CONTROL_RW 0x00000001
#define CDNS_I2C_CONTROL_MS 0x00000002
#define CDNS_I2C_CONTROL_NEA 0x00000004
#define CDNS_I2C_CONTROL_ACKEN 0x00000008
#define CDNS_I2C_CONTROL_HOLD 0x00000010
#define CDNS_I2C_CONTROL_SLVMON 0x00000020
#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
/* Status register values */
#define CDNS_I2C_STATUS_RXDV 0x00000020
#define CDNS_I2C_STATUS_TXDV 0x00000040
#define CDNS_I2C_STATUS_RXOVF 0x00000080
#define CDNS_I2C_STATUS_BA 0x00000100
/* Interrupt register fields */
#define CDNS_I2C_INTERRUPT_COMP 0x00000001
#define CDNS_I2C_INTERRUPT_DATA 0x00000002
#define CDNS_I2C_INTERRUPT_NACK 0x00000004
#define CDNS_I2C_INTERRUPT_TO 0x00000008
#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
#define CDNS_I2C_FIFO_DEPTH 16
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
#ifdef DEBUG
static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
{
int int_status;
int status;
int_status = readl(&cdns_i2c->interrupt_status);
status = readl(&cdns_i2c->status);
if (int_status || status) {
debug("Status: ");
if (int_status & CDNS_I2C_INTERRUPT_COMP)
debug("COMP ");
if (int_status & CDNS_I2C_INTERRUPT_DATA)
debug("DATA ");
if (int_status & CDNS_I2C_INTERRUPT_NACK)
debug("NACK ");
if (int_status & CDNS_I2C_INTERRUPT_TO)
debug("TO ");
if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
debug("SLVRDY ");
if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
debug("RXOVF ");
if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
debug("TXOVF ");
if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
debug("RXUNF ");
if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
debug("ARBLOST ");
if (status & CDNS_I2C_STATUS_RXDV)
debug("RXDV ");
if (status & CDNS_I2C_STATUS_TXDV)
debug("TXDV ");
if (status & CDNS_I2C_STATUS_RXOVF)
debug("RXOVF ");
if (status & CDNS_I2C_STATUS_BA)
debug("BA ");
debug("TS%d ", readl(&cdns_i2c->transfer_size));
debug("\n");
}
}
#endif
struct i2c_cdns_bus {
int id;
struct cdns_i2c_regs __iomem *regs; /* register base */
};
/** cdns_i2c_probe() - Probe method
* @dev: udevice pointer
*
* DM callback called when device is probed
*/
static int cdns_i2c_probe(struct udevice *dev)
{
struct i2c_cdns_bus *bus = dev_get_priv(dev);
bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
if (!bus->regs)
return -ENOMEM;
/* TODO: Calculate dividers based on CPU_CLK_1X */
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
/* Enable master mode, ack, and 7-bit addressing */
setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
return 0;
}
static int cdns_i2c_remove(struct udevice *dev)
{
struct i2c_cdns_bus *bus = dev_get_priv(dev);
debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
unmap_sysmem(bus->regs);
return 0;
}
/* Wait for an interrupt */
static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
{
int timeout, int_status;
for (timeout = 0; timeout < 100; timeout++) {
udelay(100);
int_status = readl(&cdns_i2c->interrupt_status);
if (int_status & mask)
break;
}
/* Clear interrupt status flags */
writel(int_status & mask, &cdns_i2c->interrupt_status);
return int_status & mask;
}
static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
if (speed != 100000) {
printf("%s, failed to set clock speed to %u\n", __func__,
speed);
return -EINVAL;
}
return 0;
}
/* Probe to see if a chip is present. */
static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
uint chip_flags)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
struct cdns_i2c_regs *regs = i2c_bus->regs;
/* Attempt to read a byte */
setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
writel(0xFF, &regs->interrupt_status);
writel(chip_addr, &regs->address);
writel(1, &regs->transfer_size);
return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
CDNS_I2C_INTERRUPT_NACK) &
CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
}
static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
u32 len, bool next_is_read)
{
u8 *cur_data = data;
struct cdns_i2c_regs *regs = i2c_bus->regs;
setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_HOLD);
/* if next is a read, we need to clear HOLD, doesn't work */
if (next_is_read)
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
writel(0xFF, &regs->interrupt_status);
writel(addr, &regs->address);
while (len--) {
writel(*(cur_data++), &regs->data);
if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
/* Release the bus */
clrbits_le32(&regs->control,
CDNS_I2C_CONTROL_HOLD);
return -ETIMEDOUT;
}
}
}
/* All done... release the bus */
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
return 0;
}
static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
u32 len)
{
u32 status;
u32 i = 0;
u8 *cur_data = data;
/* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
/* Check the hardware can handle the requested bytes */
if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
return -EINVAL;
setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
/* Start reading data */
writel(addr, &regs->address);
writel(len, &regs->transfer_size);
/* Wait for data */
do {
status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
CDNS_I2C_INTERRUPT_DATA);
if (!status) {
/* Release the bus */
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
return -ETIMEDOUT;
}
debug("Read %d bytes\n",
len - readl(&regs->transfer_size));
for (; i < len - readl(&regs->transfer_size); i++)
*(cur_data++) = readl(&regs->data);
} while (readl(&regs->transfer_size) != 0);
/* All done... release the bus */
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
#ifdef DEBUG
cdns_i2c_debug_status(regs);
#endif
return 0;
}
static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
int nmsgs)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
int ret;
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
if (msg->flags & I2C_M_RD) {
ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
msg->len);
} else {
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
msg->len, next_is_read);
}
if (ret) {
debug("i2c_write: error sending\n");
return -EREMOTEIO;
}
}
return 0;
}
static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
.probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
};
static const struct udevice_id cdns_i2c_of_match[] = {
{ .compatible = "cdns,i2c-r1p10" },
{ /* end of table */ }
};
U_BOOT_DRIVER(cdns_i2c) = {
.name = "i2c-cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
.probe = cdns_i2c_probe,
.remove = cdns_i2c_remove,
.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
.ops = &cdns_i2c_ops,
};

6
include/configs/xilinx_zynqmp.h
View File

@ -17,7 +17,6 @@
#define CONFIG_SYS_NO_FLASH
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF9010000
@ -44,8 +43,6 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Flat Device Tree Definitions */
/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
#if !defined(COUNTER_FREQUENCY)
# define COUNTER_FREQUENCY 100000000
@ -165,8 +162,7 @@
"kernel_addr=0x80000\0" \
"fdt_addr=0x7000000\0" \
"fdt_high=0x10000000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
CONFIG_KERNEL_FDT_OFST_SIZE \
"sdbootdev=0\0"\
"sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
"load mmc $sdbootdev:$partid $kernel_addr Image && " \

9
include/configs/xilinx_zynqmp_ep.h
View File

@ -15,8 +15,6 @@
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_AHCI
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
@ -24,6 +22,13 @@
#define COUNTER_FREQUENCY 4000000
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=ep108\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_EP_H */

29
include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h Normal file
View File

@ -0,0 +1,29 @@
/*
* Configuration for Xilinx ZynqMP zc1751 XM015 DC1
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
#define CONFIG_AHCI
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc1\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */

26
include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Configuration for Xilinx ZynqMP zc1751 XM016 DC2
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc2\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */

27
include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Configuration for Xilinx ZynqMP zc1751 XM019 DC5
*
* (C) Copyright 2015 Xilinx, Inc.
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x400000\0" \
"fdt_offset=0x2400000\0" \
"kernel_size=0x2000000\0" \
"fdt_size=0x80000\0" \
"board=zc1751-dc5\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */

60
include/configs/xilinx_zynqmp_zcu102.h Normal file
View File

@ -0,0 +1,60 @@
/*
* Configuration for Xilinx ZynqMP zcu102
*
* (C) Copyright 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_ZCU102_H
#define __CONFIG_ZYNQMP_ZCU102_H
#define CONFIG_ZYNQ_SDHCI1
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_NUM_I2C_BUSES 18
#define CONFIG_SYS_I2C_BUSES { \
{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
{0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
{0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
{1, {I2C_NULL_HOP} }, \
{1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
{1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
{1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
{1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
{1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
}
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_AHCI
#define CONFIG_SATA_CEVA
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102"
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x180000\0" \
"fdt_offset=0x100000\0" \
"kernel_size=0x1e00000\0" \
"fdt_size=0x80000\0" \
"board=zcu102\0"
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZCU102_H */

17
include/configs/zynq-common.h
View File

@ -39,8 +39,6 @@
#define CONFIG_ARM_DCC
#define CONFIG_ZYNQ_SERIAL
#define CONFIG_ZYNQ_GPIO
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_MII
@ -114,6 +112,7 @@
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_RESET_OFF
# define CONFIG_USB_FUNCTION_THOR
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
@ -277,15 +276,17 @@
/* Physical Memory map */
#define CONFIG_SYS_TEXT_BASE 0x4000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0
#ifndef CONFIG_NR_DRAM_BANKS
# define CONFIG_NR_DRAM_BANKS 1
#endif
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END 0x1000
#define CONFIG_SYS_MALLOC_LEN 0x1400000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)

2
include/configs/zynq_microzed.h
View File

@ -12,6 +12,8 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_USB
#include <configs/zynq-common.h>
#endif /* __CONFIG_ZYNQ_MICROZED_H */