QuadSPI: use QSPI_CMD_xx instead of flash opcodes
Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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@ -29,19 +29,19 @@
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#define SEQID_PP 6
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#define SEQID_RDID 7
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/* Flash opcodes */
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#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
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#define OPCODE_RDSR 0x05 /* Read status register */
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#define OPCODE_WREN 0x06 /* Write enable */
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#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
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#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define OPCODE_RDID 0x9f /* Read JEDEC ID */
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/* QSPI CMD */
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#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
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#define QSPI_CMD_RDSR 0x05 /* Read status register */
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#define QSPI_CMD_WREN 0x06 /* Write enable */
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#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
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#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
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#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
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#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
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#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
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#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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#ifdef CONFIG_SYS_FSL_QSPI_LE
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#define qspi_read32 in_le32
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@ -94,7 +94,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Write Enable */
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lut_base = SEQID_WREN * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_WREN) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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@ -103,13 +103,15 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Fast Read */
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lut_base = SEQID_FAST_READ * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base],
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OPRND0(QSPI_CMD_FAST_READ_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
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OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
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INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
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INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
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INSTR1(LUT_READ));
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@ -118,7 +120,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Read Status */
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lut_base = SEQID_RDSR * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDSR) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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qspi_write32(®s->lut[lut_base + 1], 0);
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@ -128,11 +130,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Erase a sector */
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lut_base = SEQID_SE * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE_4B) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], 0);
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@ -141,7 +143,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Erase the whole chip */
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lut_base = SEQID_CHIP_ERASE * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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@ -150,11 +152,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* Page Program */
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lut_base = SEQID_PP * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
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@ -164,7 +166,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
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/* READ ID */
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lut_base = SEQID_RDID * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDID) |
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qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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qspi_write32(®s->lut[lut_base + 1], 0);
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@ -454,22 +456,22 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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return 0;
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}
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if (qspi->cur_seqid == OPCODE_FAST_READ) {
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if (qspi->cur_seqid == QSPI_CMD_FAST_READ) {
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qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
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} else if (qspi->cur_seqid == OPCODE_SE) {
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} else if (qspi->cur_seqid == QSPI_CMD_SE) {
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qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
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qspi_op_se(qspi);
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} else if (qspi->cur_seqid == OPCODE_PP) {
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} else if (qspi->cur_seqid == QSPI_CMD_PP) {
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pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
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}
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}
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if (din) {
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if (qspi->cur_seqid == OPCODE_FAST_READ)
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if (qspi->cur_seqid == QSPI_CMD_FAST_READ)
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qspi_op_read(qspi, din, bytes);
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else if (qspi->cur_seqid == OPCODE_RDID)
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else if (qspi->cur_seqid == QSPI_CMD_RDID)
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qspi_op_rdid(qspi, din, bytes);
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else if (qspi->cur_seqid == OPCODE_RDSR)
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else if (qspi->cur_seqid == QSPI_CMD_RDSR)
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qspi_op_rdsr(qspi, din);
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}
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