Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver
and adapted board configs TQM5200 and yosemite accordingly. This commit also makes the maximum number of root hub ports configurable (CFG_USB_OHCI_MAX_ROOT_PORTS).
This commit is contained in:
parent
98280e3d43
commit
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@ -28,7 +28,7 @@ LIB = lib$(CPU).a
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START = start.o
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ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
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OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
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loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
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loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
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all: .depend $(START) $(ASOBJS) $(LIB)
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@ -31,7 +31,8 @@ COBJS = 405gp_pci.o 4xx_enet.o \
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bedbug_405.o commproc.o \
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cpu.o cpu_init.o i2c.o interrupts.o \
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miiphy.o sdram.o serial.o \
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spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
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spd_sdram.o speed.o traps.o \
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usb_ohci.o usbdev.o usb.o
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OBJS = $(AOBJS) $(COBJS)
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@ -45,6 +45,7 @@
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#ifdef CONFIG_USB_OHCI
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/* mk: are these really required? */
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#if defined(CONFIG_S3C2400)
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# include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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@ -53,6 +54,8 @@
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# include <asm/arch/hardware.h>
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#elif defined(CONFIG_CPU_MONAHANS)
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# include <asm/arch/pxa-regs.h>
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#elif defined(CONFIG_MPC5200)
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# include <mpc5xxx.h>
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#endif
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#include <malloc.h>
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@ -557,8 +560,10 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
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* the link from the ed still points to another operational ed or 0
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* so the HC can eventually finish the processing of the unlinked ed */
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static int ep_unlink (ohci_t *ohci, ed_t *ed)
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static int ep_unlink (ohci_t *ohci, ed_t *edi)
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{
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volatile ed_t *ed = edi;
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ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
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switch (ed->type) {
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@ -825,6 +830,9 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
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} else
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td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
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}
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#ifdef CONFIG_MPC5200
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td_list->hwNextTD = 0;
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#endif
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}
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td_list->next_dl_td = td_rev;
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@ -1448,7 +1456,8 @@ static int hc_reset (ohci_t *ohci)
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readl(&ohci->regs->control));
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/* Reset USB (needed by some controllers) */
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writel (0, &ohci->regs->control);
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ohci->hc_control = 0;
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writel (ohci->hc_control, &ohci->regs->control);
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/* HC Reset requires max 10 us delay */
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writel (OHCI_HCR, &ohci->regs->cmdstatus);
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@ -113,7 +113,9 @@ struct td {
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__u32 hwNextTD; /* Next TD Pointer */
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__u32 hwBE; /* Memory Buffer End Pointer */
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/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
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__u16 hwPSW[MAXPSW];
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/* #endif */
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__u8 unused;
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__u8 index;
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struct ed *ed;
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@ -137,8 +139,13 @@ typedef struct td td_t;
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#define NUM_INTS 32 /* part of the OHCI standard */
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struct ohci_hcca {
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__u32 int_table[NUM_INTS]; /* Interrupt ED table */
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#if defined(CONFIG_MPC5200)
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__u16 pad1; /* set to 0 on each frame_no change */
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__u16 frame_no; /* current frame number */
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#else
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__u16 frame_no; /* current frame number */
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__u16 pad1; /* set to 0 on each frame_no change */
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#endif
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__u32 done_head; /* info returned for an interrupt */
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u8 reserved_for_hc[116];
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} __attribute((aligned(256)));
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@ -147,7 +154,9 @@ struct ohci_hcca {
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/*
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* Maximum number of root hub ports.
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*/
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#define MAX_ROOT_PORTS 3 /* maximum OHCI root hub ports */
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#ifndef CFG_USB_OHCI_MAX_ROOT_PORTS
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# error "CFG_USB_OHCI_MAX_ROOT_PORTS undefined!"
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#endif
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/*
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* This is the structure of the OHCI controller's memory mapped I/O
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@ -181,7 +190,7 @@ struct ohci_regs {
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__u32 a;
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__u32 b;
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__u32 status;
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__u32 portstatus[MAX_ROOT_PORTS];
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__u32 portstatus[CFG_USB_OHCI_MAX_ROOT_PORTS];
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} roothub;
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} __attribute((aligned(32)));
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@ -128,6 +128,13 @@
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#define CONFIG_USB_OHCI
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#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
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#define CONFIG_USB_STORAGE
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#undef CFG_USB_OHCI_BOARD_INIT
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#define CFG_USB_OHCI_CPU_INIT
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#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
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#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#else
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#define ADD_USB_CMD 0
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#endif
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@ -111,6 +111,7 @@
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#define CFG_USB_OHCI_CPU_INIT 1
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#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
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#define CFG_USB_OHCI_SLOT_NAME "delta"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
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#define LITTLEENDIAN 1 /* used by usb_ohci.c */
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@ -111,6 +111,7 @@
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#define CFG_USB_OHCI_CPU_INIT 1
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#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
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#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#undef CONFIG_HARD_I2C
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@ -88,6 +88,7 @@
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#define CFG_USB_OHCI_CPU_INIT 1
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#define CFG_USB_OHCI_REGS_BASE S3C24X0_USB_HOST_BASE
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#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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/*
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* Size of malloc() pool
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@ -216,6 +216,12 @@
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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#undef CFG_USB_OHCI_BOARD_INIT
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#define CFG_USB_OHCI_CPU_INIT 1
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#define CFG_USB_OHCI_REGS_BASE (CFG_PERIPHERAL_BASE | 0x1000)
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#define CFG_USB_OHCI_SLOT_NAME "ppc440"
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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/*Comment this out to enable USB 1.1 device*/
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440EP*/
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