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Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

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With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
This commit is contained in:
Joe D'Abbraccio 2008-03-24 13:00:59 -04:00 committed by Kim Phillips
parent a7ba32d480
commit 507e2d79c9
1 changed files with 1 additions and 1 deletions
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2
include/configs/MPC8349ITX.h
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@ -156,7 +156,7 @@
#define CFG_MEMTEST_END 0x2000
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/