Merge git://www.denx.de/git/u-boot-marvell
This commit is contained in:
Tom Rini
commit
4edc31c593
@ -30,6 +30,8 @@
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#include <asm/arch/soc.h>
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#include <linux/compat.h>
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#include <linux/mbus.h>
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#include <asm-generic/gpio.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -314,6 +316,8 @@ do { \
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#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
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#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
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#define MVPP22_BM_MC_RLS_REG 0x64d4
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#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
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#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
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/* TX Scheduler registers */
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#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
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@ -615,10 +619,10 @@ enum mv_netc_lanes {
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#define MVPP2_MAX_TXD 16
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/* Amount of Tx descriptors that can be reserved at once by CPU */
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#define MVPP2_CPU_DESC_CHUNK 64
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#define MVPP2_CPU_DESC_CHUNK 16
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/* Max number of Tx descriptors in each aggregated queue */
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#define MVPP2_AGGR_TXQ_SIZE 256
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#define MVPP2_AGGR_TXQ_SIZE 16
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/* Descriptor aligned size */
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#define MVPP2_DESC_ALIGNED_SIZE 32
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@ -940,6 +944,7 @@ struct mvpp2 {
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struct mii_dev *bus;
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int probe_done;
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u8 num_ports;
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};
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struct mvpp2_pcpu_stats {
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@ -985,6 +990,10 @@ struct mvpp2_port {
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phy_interface_t phy_interface;
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int phy_node;
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int phyaddr;
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#ifdef CONFIG_DM_GPIO
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struct gpio_desc phy_reset_gpio;
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struct gpio_desc phy_tx_disable_gpio;
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#endif
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int init;
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unsigned int link;
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unsigned int duplex;
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@ -2587,6 +2596,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
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mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
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lower_32_bits(bm_pool->dma_addr));
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if (priv->hw_version == MVPP22)
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mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
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(upper_32_bits(bm_pool->dma_addr) &
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MVPP22_BM_POOL_BASE_HIGH_MASK));
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mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
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val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
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@ -2662,7 +2675,7 @@ static int mvpp2_bm_pools_init(struct udevice *dev,
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err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
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if (err)
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goto err_unroll_pools;
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mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
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mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
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}
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return 0;
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@ -2848,9 +2861,6 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
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}
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}
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mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
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MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
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return new_pool;
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}
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@ -3057,10 +3067,6 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
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val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/*
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* Configure GIG MAC to 1000Base-X mode connected to a fiber
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@ -3103,10 +3109,6 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
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val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/* configure GIG MAC to SGMII mode */
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val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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@ -3145,10 +3147,6 @@ static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
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val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/* configure GIG MAC to SGMII mode */
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val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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@ -4686,20 +4684,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
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port->rxqs[queue] = rxq;
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}
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/* Configure Rx queue group interrupt for this port */
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if (priv->hw_version == MVPP21) {
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mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
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CONFIG_MV_ETH_RXQ);
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} else {
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u32 val;
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val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
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mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
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val = (CONFIG_MV_ETH_RXQ <<
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MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
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mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
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}
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/* Create Rx descriptor rings */
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for (queue = 0; queue < rxq_number; queue++) {
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@ -4734,10 +4718,11 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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{
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int port_node = dev_of_offset(dev);
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const char *phy_mode_str;
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int phy_node;
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int phy_node, mdio_off, cp_node;
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u32 id;
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u32 phyaddr = 0;
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int phy_mode = -1;
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u64 mdio_addr;
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phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
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@ -4747,6 +4732,28 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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dev_err(&pdev->dev, "could not find phy address\n");
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return -1;
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}
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mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
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/* TODO: This WA for mdio issue. U-boot 2017 don't have
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* mdio driver and on MACHIATOBin board ports from CP1
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* connected to mdio on CP0.
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* WA is to get mdio address from phy handler parent
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* base address. WA should be removed after
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* mdio driver implementation.
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*/
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mdio_addr = fdtdec_get_uint(gd->fdt_blob,
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mdio_off, "reg", 0);
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cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
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mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
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cp_node);
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port->priv->mdio_base = (void *)mdio_addr;
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if (port->priv->mdio_base < 0) {
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dev_err(&pdev->dev, "could not find mdio base address\n");
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return -1;
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}
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} else {
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phy_node = 0;
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}
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@ -4765,6 +4772,13 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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return -EINVAL;
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}
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#ifdef CONFIG_DM_GPIO
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gpio_request_by_name(dev, "phy-reset-gpios", 0,
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&port->phy_reset_gpio, GPIOD_IS_OUT);
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gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
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&port->phy_tx_disable_gpio, GPIOD_IS_OUT);
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#endif
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/*
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* ToDo:
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* Not sure if this DT property "phy-speed" will get accepted, so
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@ -4786,6 +4800,21 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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return 0;
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}
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#ifdef CONFIG_DM_GPIO
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/* Port GPIO initialization */
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static void mvpp2_gpio_init(struct mvpp2_port *port)
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{
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if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
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dm_gpio_set_value(&port->phy_reset_gpio, 0);
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udelay(1000);
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dm_gpio_set_value(&port->phy_reset_gpio, 1);
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}
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if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
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dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
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}
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#endif
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/* Ports initialization */
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static int mvpp2_port_probe(struct udevice *dev,
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struct mvpp2_port *port,
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@ -4804,7 +4833,12 @@ static int mvpp2_port_probe(struct udevice *dev,
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}
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mvpp2_port_power_up(port);
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#ifdef CONFIG_DM_GPIO
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mvpp2_gpio_init(port);
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#endif
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priv->port_list[port->id] = port;
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priv->num_ports++;
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return 0;
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}
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@ -4969,13 +5003,14 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
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return -EINVAL;
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}
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/* MBUS windows configuration */
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dram_target_info = mvebu_mbus_dram_info();
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if (dram_target_info)
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mvpp2_conf_mbus_windows(dram_target_info, priv);
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if (priv->hw_version == MVPP22)
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mvpp2_axi_init(priv);
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else {
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/* MBUS windows configuration */
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dram_target_info = mvebu_mbus_dram_info();
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if (dram_target_info)
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mvpp2_conf_mbus_windows(dram_target_info, priv);
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}
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if (priv->hw_version == MVPP21) {
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/* Disable HW PHY polling */
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@ -5012,25 +5047,6 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
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if (priv->hw_version == MVPP22)
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mvpp2_tx_fifo_init(priv);
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/* Reset Rx queue group interrupt configuration */
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for (i = 0; i < MVPP2_MAX_PORTS; i++) {
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if (priv->hw_version == MVPP21) {
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mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
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CONFIG_MV_ETH_RXQ);
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continue;
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} else {
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u32 val;
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val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
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mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
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val = (CONFIG_MV_ETH_RXQ <<
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MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
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mvpp2_write(priv,
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MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
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}
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}
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if (priv->hw_version == MVPP21)
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writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
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priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
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@ -5176,21 +5192,10 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
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int pool, rx_bytes, err;
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int rx_received;
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struct mvpp2_rx_queue *rxq;
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u32 cause_rx_tx, cause_rx, cause_misc;
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u8 *data;
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cause_rx_tx = mvpp2_read(port->priv,
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MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
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cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
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cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
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if (!cause_rx_tx && !cause_misc)
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return 0;
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cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
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/* Process RX packets */
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cause_rx |= port->pending_cause_rx;
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rxq = mvpp2_get_rx_queue(port, cause_rx);
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rxq = port->rxqs[0];
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/* Get number of received packets and clamp the to-do */
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rx_received = mvpp2_rxq_received(port, rxq->id);
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@ -5246,21 +5251,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
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return rx_bytes;
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}
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/* Drain Txq */
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static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
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int enable)
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{
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u32 val;
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mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
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val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
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if (enable)
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val |= MVPP2_TXQ_DRAIN_EN_MASK;
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else
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val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
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mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
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}
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static int mvpp2_send(struct udevice *dev, void *packet, int length)
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{
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struct mvpp2_port *port = dev_get_priv(dev);
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@ -5304,9 +5294,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
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tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
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} while (tx_done);
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/* Enable TXQ drain */
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mvpp2_txq_drain(port, txq, 1);
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timeout = 0;
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do {
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if (timeout++ > 10000) {
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@ -5316,9 +5303,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
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tx_done = mvpp2_txq_sent_desc_proc(port, txq);
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} while (!tx_done);
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/* Disable TXQ drain */
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mvpp2_txq_drain(port, txq, 0);
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return 0;
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}
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@ -5469,10 +5453,8 @@ static int mvpp2_probe(struct udevice *dev)
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int err;
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/* Only call the probe function for the parent once */
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if (!priv->probe_done) {
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if (!priv->probe_done)
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err = mvpp2_base_probe(dev->parent);
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priv->probe_done = 1;
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}
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port->priv = dev_get_priv(dev->parent);
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@ -5510,11 +5492,15 @@ static int mvpp2_probe(struct udevice *dev)
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gop_port_init(port);
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}
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/* Initialize network controller */
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err = mvpp2_init(dev, priv);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to initialize controller\n");
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return err;
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if (!priv->probe_done) {
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/* Initialize network controller */
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err = mvpp2_init(dev, priv);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to initialize controller\n");
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return err;
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}
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priv->num_ports = 0;
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priv->probe_done = 1;
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}
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err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
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@ -5542,6 +5528,11 @@ static int mvpp2_remove(struct udevice *dev)
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struct mvpp2 *priv = port->priv;
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int i;
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priv->num_ports--;
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if (priv->num_ports)
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return 0;
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for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
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mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
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