ARM: Factor out reusable psci_cpu_entry
_sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -165,6 +165,15 @@ ENTRY(psci_disable_smp)
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ENDPROC(psci_disable_smp)
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.weak psci_disable_smp
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ENTRY(psci_enable_smp)
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mrc p15, 0, r0, c1, c0, 1 @ ACTLR
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orr r0, r0, #(1 << 6) @ Set SMP bit
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mcr p15, 0, r0, c1, c0, 1 @ ACTLR
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isb
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bx lr
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ENDPROC(psci_enable_smp)
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.weak psci_enable_smp
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ENTRY(psci_cpu_off_common)
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push {lr}
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@ -184,4 +193,18 @@ ENTRY(psci_cpu_off_common)
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bx lr
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ENDPROC(psci_cpu_off_common)
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ENTRY(psci_cpu_entry)
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bl psci_enable_smp
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bl _nonsec_init
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adr r0, _psci_target_pc
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ldr r0, [r0]
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b _do_nonsec_entry
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ENDPROC(psci_cpu_entry)
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.globl _psci_target_pc
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_psci_target_pc:
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.word 0
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.popsection
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@ -139,7 +139,7 @@ out: mcr p15, 0, r7, c1, c1, 0
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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adr r0, _target_pc
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ldr r0, =_psci_target_pc
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str r2, [r0]
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dsb
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@ -151,7 +151,7 @@ psci_cpu_on:
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mov r4, #1
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lsl r4, r4, r1
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adr r6, _sunxi_cpu_entry
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ldr r6, =psci_cpu_entry
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str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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@ Assert reset on target CPU
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@ -197,22 +197,6 @@ psci_cpu_on:
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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mov pc, lr
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_target_pc:
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.word 0
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_sunxi_cpu_entry:
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@ Set SMP bit
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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isb
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bl _nonsec_init
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adr r0, _target_pc
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ldr r0, [r0]
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b _do_nonsec_entry
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.globl psci_cpu_off
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psci_cpu_off:
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bl psci_cpu_off_common
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