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mpc83xx: Introduce ARCH_MPC830*

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Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-01-21 09:17:24 +01:00
parent 748198cb8d
commit 4bc97a3b81
20 changed files with 66 additions and 62 deletions
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17
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -10,6 +10,7 @@ choice
config TARGET_MPC8308_P1M
bool "Support mpc8308_p1m"
select ARCH_MPC8308
config TARGET_SBC8349
bool "Support sbc8349"
@ -22,6 +23,7 @@ config TARGET_VME8349
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB
@ -74,6 +76,8 @@ config TARGET_KM8360
config TARGET_SUVD3
bool "Support suvd3"
select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1"
select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1"
imply CMD_CRAMFS
imply FS_CRAMFS
@ -87,15 +91,28 @@ config TARGET_TQM834X
config TARGET_HRCON
bool "Support hrcon"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_PCA953X
endchoice
config ARCH_MPC830X
bool
config ARCH_MPC8308
bool
select ARCH_MPC830X
config ARCH_MPC8309
bool
select ARCH_MPC830X
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"

2
arch/powerpc/cpu/mpc83xx/spd_sdram.c
View File

@ -31,7 +31,7 @@ void board_add_ram_info(int use_default)
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)

38
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -85,12 +85,12 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
@ -107,7 +107,7 @@ int get_clocks(void)
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
u32 enc_clk;
#endif
u32 lbiu_clk;
@ -122,7 +122,7 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
@ -155,7 +155,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
@ -176,7 +176,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
@ -197,7 +197,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
@ -252,7 +252,7 @@ int get_clocks(void)
return -6;
}
#endif
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@ -317,20 +317,20 @@ int get_clocks(void)
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
@ -448,12 +448,12 @@ int get_clocks(void)
#endif
gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
@ -470,7 +470,7 @@ int get_clocks(void)
#if !defined(CONFIG_MPC832x)
gd->arch.i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
gd->arch.enc_clk = enc_clk;
#endif
gd->arch.lbiu_clk = lbiu_clk;
@ -483,7 +483,7 @@ int get_clocks(void)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
@ -540,7 +540,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" DDR Secondary: %-4s MHz\n",
strmhz(buf, gd->arch.mem_sec_clk));
#endif
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
printf(" SEC: %-4s MHz\n",
strmhz(buf, gd->arch.enc_clk));
#endif
@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
@ -566,7 +566,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
strmhz(buf, gd->arch.tsec2_clk));
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
#endif
@ -574,7 +574,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));

2
arch/powerpc/include/asm/arch-mpc83xx/gpio.h
View File

@ -6,7 +6,7 @@
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \
#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_MPC8315)
#define MPC83XX_GPIO_CTRLRS 1
#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)

2
arch/powerpc/include/asm/fsl_lbc.h
View File

@ -133,7 +133,7 @@ void lbc_sdram_init(void);
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
#if !defined(CONFIG_MPC8308)
#if !defined(CONFIG_ARCH_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#endif

6
arch/powerpc/include/asm/global_data.h
View File

@ -35,12 +35,12 @@ struct arch_global_data {
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
# elif defined(CONFIG_MPC8309)
# elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
# endif
# if defined(CONFIG_MPC834x)
@ -53,7 +53,7 @@ struct arch_global_data {
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;

10
arch/powerpc/include/asm/immap_83xx.h
View File

@ -59,12 +59,12 @@ typedef struct sysconf83xx {
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
#if defined(CONFIG_MPC830x)
#if defined(CONFIG_ARCH_MPC830X)
u32 sdhccr; /* eSDHC Control Registers for MPC830x */
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
#if defined(CONFIG_MPC8309)
#if defined(CONFIG_ARCH_MPC8309)
u32 can_dbg_ctrl;
u32 res9a;
u32 gpr1;
@ -604,7 +604,7 @@ typedef struct serdes83xx {
* On Chip ROM
*/
typedef struct rom83xx {
#if defined(CONFIG_MPC8309)
#if defined(CONFIG_ARCH_MPC8309)
u8 mem[0x8000];
#else
u8 mem[0x10000];
@ -714,7 +714,7 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@ -879,7 +879,7 @@ typedef struct immap {
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */

2
arch/powerpc/include/asm/mpc8xxx_spi.h
View File

@ -10,7 +10,7 @@
#include <asm/types.h>
#if defined(CONFIG_MPC8308) || \
#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_MPC8313) || \
defined(CONFIG_MPC8315) || \
defined(CONFIG_MPC834x) || \

2
board/keymile/km83xx/km83xx.c
View File

@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
#elif !defined(CONFIG_MPC8309)
#elif !defined(CONFIG_ARCH_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */

2
drivers/qe/qe.c
View File

@ -119,7 +119,7 @@ static void qe_sdma_init(void)
*/
static u8 thread_snum[] = {
/* Evthreads 16-29 are not supported in MPC8309 */
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,

4
drivers/ram/mpc83xx_sdram.c
View File

@ -179,7 +179,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_NEVER:
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_MPC830x) &&
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
@ -210,7 +210,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_NEVER:
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_MPC830x) &&
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {

2
include/configs/MPC8308RDB.h
View File

@ -12,8 +12,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR

2
include/configs/hrcon.h
View File

@ -13,8 +13,6 @@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_HRCON 1 /* HRCON board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR

2
include/configs/km/km8309-common.h
View File

@ -14,8 +14,6 @@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"

2
include/configs/km/km83xx-common.h
View File

@ -135,7 +135,7 @@
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#if !defined(CONFIG_MPC8309)
#if !defined(CONFIG_ARCH_MPC8309)
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#endif

2
include/configs/mpc8308_p1m.h
View File

@ -12,8 +12,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
/*
* On-board devices

2
include/configs/strider.h
View File

@ -13,8 +13,6 @@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_STRIDER 1 /* STRIDER board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR

2
include/linux/immap_qe.h
View File

@ -16,7 +16,7 @@
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28

24
include/mpc83xx.h
View File

@ -129,7 +129,7 @@
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
/* TSEC data priority */
@ -336,7 +336,7 @@
#define SICRH_SPI 0x00000003
#define SICRH_SPI_SD 0x00000001
#elif defined(CONFIG_MPC8308)
#elif defined(CONFIG_ARCH_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
#define SICRL_SPI_PF1 (1 << 28)
@ -384,7 +384,7 @@
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
/* SICR_1 */
#define SICR_1_UART1_UART1S (0 << (30-2))
#define SICR_1_UART1_UART1RTS (1 << (30-2))
@ -639,7 +639,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
@ -654,7 +654,7 @@
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
@ -765,7 +765,7 @@
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
@ -818,7 +818,7 @@
/*
* RSR - Reset Status Register
*/
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
@ -986,7 +986,7 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@ -1071,7 +1071,7 @@
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
#elif defined(CONFIG_MPC8309)
#elif defined(CONFIG_ARCH_MPC8309)
/* SCCR bits - MPC8309 specific */
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
@ -1117,7 +1117,7 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
@ -1239,14 +1239,14 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
#else
#define SDRAM_CFG_32_BE 0x00080000
#endif
#if !defined(CONFIG_MPC8308)
#if !defined(CONFIG_ARCH_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
#endif
#define SDRAM_CFG_NCAP 0x00020000

3
scripts/config_whitelist.txt
View File

@ -1220,9 +1220,6 @@ CONFIG_MMC_SPI_SPEED
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
CONFIG_MPC8308
CONFIG_MPC8309
CONFIG_MPC830x
CONFIG_MPC8313
CONFIG_MPC8313ERDB
CONFIG_MPC8315