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clk: renesas: Fix swapped div and mul in debug output on Gen2

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The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-03-18 05:38:08 +01:00 committed by Marek Vasut
parent 45b01b462f
commit 4b135d5464
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/renesas/clk-rcar-gen2.c
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@ -121,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
case CLK_TYPE_FF: case CLK_TYPE_FF:
rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
__func__, __LINE__, __func__, __LINE__,
core->parent, core->mult, core->div, rate); core->parent, core->mult, core->div, rate);
return rate; return rate;