ppc: Drop t4qds and b4860qds references

These boards have been removed. Drop the config file and other references.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2021-08-01 18:54:42 -06:00 committed by Tom Rini
parent 666671ecc3
commit 4a753fbcee
4 changed files with 2 additions and 696 deletions

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@ -413,11 +413,11 @@ jobs:
non_fsl_ppc: non_fsl_ppc:
BUILDMAN: "powerpc -x freescale" BUILDMAN: "powerpc -x freescale"
mpc85xx_freescale: mpc85xx_freescale:
BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*" BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
t208xrdb_corenet_ds: t208xrdb_corenet_ds:
BUILDMAN: "t208xrdb corenet_ds" BUILDMAN: "t208xrdb corenet_ds"
fsl_ppc: fsl_ppc:
BUILDMAN: "t4qds b4860qds mpc83xx&freescale" BUILDMAN: "mpc83xx&freescale"
t102x: t102x:
BUILDMAN: "t102*" BUILDMAN: "t102*"
p1_p2_rdb_pc: p1_p2_rdb_pc:

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@ -1,453 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0+
B4860QDS
========
The B4860QDS is a Freescale reference board that hosts the B4860 SoC
(and variants).
B4860 Overview
--------------
The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
StarCore and Power Architecture® cores. It targets the broadband wireless
infrastructure and builds upon the proven success of the existing multicore
DSPs and Power CPUs. It is designed to bolster the rapidly changing and
expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
The B4860 is a highly-integrated StarCore and Power Architecture processor that
contains:
* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
for wireless base station applications
* Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
* Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
* MAPLE-B3 hardware acceleration-for forward error correction schemes including
Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
acceleration
* CoreNet fabric that fully supports coherency using MESI protocol between the
e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and bandwidth
allocation amongst CoreNet endpoints.
* Data Path Acceleration Architecture, which includes the following:
* Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
* Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
* Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
* RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
and outbound). Supports types 5, 6 (outbound only)
* Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The 9856-Kbyte
internal memory space includes the following:
* 32 Kbyte L1 ICache per e6500/SC3900 core
* 32 Kbyte L1 DCache per e6500/SC3900 core
* 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
* 2048 Kbyte unified L2 cache for the e6500 cluster
* Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
* Sixteen 10-GHz SerDes lanes serving:
* Two Serial RapidIO interfaces
* Each supports up to 4 lanes and a total of up to 8 lanes
* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
glue-less antenna connection
* Two 10-Gbit Ethernet controllers (10GEC)
* Six 1G/2.5-Gbit Ethernet controllers for network communications
* PCI Express controller
* Debug (Aurora)
* Two OCeaN DMAs
* Various system peripherals
* 182 32-bit timers
B4860QDS Overview
-----------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
copper connectors for Stand-alone mode and to the 1000Base-X over AMC
MicroTCA connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset configuration
reset source. The RCW source is set by appropriate DIP-switches.
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1,2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
frequency - total four refclk, including CPRI clock scheme.
B4420 Personality
-----------------
B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
and reduced target frequencies.
Key differences between B4860 and B4420
---------------------------------------
B4420 has:
1. Less e6500 cores: 1 cluster with 2 e6500 cores
2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G
B4860QDS Default Settings
-------------------------
Switch Settings
^^^^^^^^^^^^^^^
.. code-block:: none
SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
SW2 ON ON ON ON ON ON OFF OFF
SW3 OFF OFF OFF ON OFF OFF ON OFF
SW5 OFF OFF OFF OFF OFF OFF ON ON
Note:
- PCIe slots modes: All the PCIe devices work as Root Complex.
- Boot location: NOR flash.
SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
NAND boot::
SW1 [1.1] = 0
SW2 [1.1] = 1
SW3 [1:4] = 0001
NOR boot::
SW1 [1.1] = 1
SW2 [1.1] = 0
SW3 [1:4] = 1000
B4420QDS Default Settings
-------------------------
Switch Settings
^^^^^^^^^^^^^^^
.. code-block:: none
SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
SW2 ON OFF ON OFF ON ON OFF OFF
SW3 OFF OFF OFF ON OFF OFF ON OFF
SW5 OFF OFF OFF OFF OFF OFF ON ON
Note:
- PCIe slots modes: All the PCIe devices work as Root Complex.
- Boot location: NOR flash.
SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
NAND boot::
SW1 [1.1] = 0
SW2 [1.1] = 1
SW3 [1:4] = 0001
NOR boot::
SW1 [1.1] = 1
SW2 [1.1] = 0
SW3 [1:4] = 1000
Memory map on B4860QDS
----------------------
The addresses in brackets are physical addresses.
============= ============= =============== =======
Start Address End Address Description Size
============= ============= =============== =======
0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
============= ============= =============== =======
Memory map on B4420QDS
----------------------
The addresses in brackets are physical addresses.
============= ============= =============== =======
Start Address End Address Description Size
============= ============= =============== =======
0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
============= ============= =============== =======
NOR Flash memory Map on B4860 and B4420QDS
------------------------------------------
============= ============= ============================== =========
Start End Definition Size
============= ============= ============================== =========
0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
0xEC000000 0xEC01FFFF RCW (current bank) 128KB
============= ============= ============================== =========
Various Software configurations/environment variables/commands
--------------------------------------------------------------
The below commands apply to both B4860QDS and B4420QDS.
U-Boot environment variable hwconfig
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The default hwconfig is:
.. code-block:: none
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
Note: For USB gadget set "dr_mode=peripheral"
FMAN Ucode versions
^^^^^^^^^^^^^^^^^^^
fsl_fman_ucode_B4860_106_3_6.bin
Switching to alternate bank
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Commands for switching to alternate bank.
1. To change from vbank0 to vbank2
.. code-block:: none
=> qixis_reset altbank (it will boot using vbank2)
2. To change from vbank2 to vbank0
.. code-block:: none
=> qixis reset (it will boot using vbank0)
To change personality of board
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
For changing personality from B4860 to B4420
1. Boot from vbank0
2. Flash vbank2 with b4420 rcw and U-Boot
3. Give following commands to uboot prompt
.. code-block:: none
=> mw.b ffdf0040 0x30;
=> mw.b ffdf0010 0x00;
=> mw.b ffdf0062 0x02;
=> mw.b ffdf0050 0x02;
=> mw.b ffdf0010 0x30;
=> reset
Note:
- Power off cycle will lead to default switch settings.
- 0xffdf0000 is the address of the QIXIS FPGA.
Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To change from NOR to NAND boot give following command on uboot prompt
.. code-block:: none
=> mw.b ffdf0040 0x30
=> mw.b ffdf0010 0x00
=> mw.b 0xffdf0050 0x08
=> mw.b 0xffdf0060 0x82
=> mw.b ffdf0061 0x00
=> mw.b ffdf0010 0x30
=> reset
To change from NAND to NOR boot give following command on uboot prompt:
.. code-block:: none
=> mw.b ffdf0040 0x30
=> mw.b ffdf0010 0x00
=> mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
=> mw.b 0xffdf0060 0x12
=> mw.b ffdf0061 0x01
=> mw.b ffdf0010 0x30
=> reset
Note:
- Power off cycle will lead to default switch settings.
- 0xffdf0000 is the address of the QIXIS FPGA.
Ethernet interfaces for B4860QDS
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Serdes protocosl tested:
* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
* 0x2a, 0xb2 (serdes1, serdes2)
When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
SGMII on SGMII riser card.
Under U-Boot these network interfaces are recognized as::
FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
On Linux the interfaces are renamed as::
eth2 -> fm1-gb2
eth3 -> fm1-gb3
eth4 -> fm1-gb4
eth5 -> fm1-gb5
RCW and Ethernet interfaces for B4420QDS
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Serdes protocosl tested:
* 0x18, 0x9e (serdes1, serdes2)
Under U-Boot these network interfaces are recognized as::
FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
On Linux the interfaces are renamed as::
eth2 -> fm1-gb2
eth3 -> fm1-gb3
NAND boot with 2 Stage boot loader
----------------------------------
PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
SPL further initialise DDR using SPD and environment variables and copy
U-Boot(768 KB) from flash to DDR.
Finally SPL transer control to U-Boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework during boot:
+----------------------------------------------+
|Area | Address |
+----------------------------------------------+
|Secure boot | 0xFFFC0000 (32KB) |
|headers | |
+----------------------------------------------+
|GD, BD | 0xFFFC8000 (4KB) |
+----------------------------------------------+
|ENV | 0xFFFC9000 (8KB) |
+----------------------------------------------+
|HEAP | 0xFFFCB000 (30KB) |
+----------------------------------------------+
|STACK | 0xFFFD8000 (22KB) |
+----------------------------------------------+
|U-Boot SPL | 0xFFFD8000 (160KB) |
+----------------------------------------------+
NAND Flash memory Map on B4860 and B4420QDS
-------------------------------------------
============= ============= ============================= =====
Start End Definition Size
============= ============= ============================= =====
0x000000 0x0FFFFF U-Boot 1MB
0x140000 0x15FFFF U-Boot env 128KB
0x1A0000 0x1BFFFF FMAN Ucode 128KB
============= ============= ============================= =====

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@ -6,7 +6,6 @@ Freescale
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
b4860qds
imx8mm_evk imx8mm_evk
imx8mn_evk imx8mn_evk
imx8mp_evk imx8mp_evk

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@ -1,240 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
/*
* Corenet DS style board configuration file
*/
#ifndef __T4QDS_H
#define __T4QDS_H
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_ENABLE_36BIT_PHYS
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE (512 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_DDR_SPD
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#define CONFIG_LBA48
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_ETHPRIME "FM1@DTSEC1"
#endif
/*
* Environment
*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
#endif /* __CONFIG_H */