net: sh_eth: modify the definitions of regsiter
The previous code had many similar definitions in each CPU. This patch borrows from the sh_eth driver of Linux kernel. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This commit is contained in:
Yoshihiro Shimoda
Joe Hershberger
parent
262350932c
commit
49afb8cafc
@ -76,8 +76,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
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/* Restart the transmitter if disabled */
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if (!(inl(EDTRR(port)) & EDTRR_TRNS))
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outl(EDTRR_TRNS, EDTRR(port));
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if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
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sh_eth_write(eth, EDTRR_TRNS, EDTRR);
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/* Wait until packet is transmitted */
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timeout = TIMEOUT_CNT;
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@ -129,25 +129,24 @@ int sh_eth_recv(struct eth_device *dev)
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}
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/* Restart the receiver if disabled */
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if (!(inl(EDRRR(port)) & EDRRR_R))
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outl(EDRRR_R, EDRRR(port));
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if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
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sh_eth_write(eth, EDRRR_R, EDRRR);
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return len;
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}
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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#if defined(SH_ETH_TYPE_GETHER)
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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outl(EDSR_ENALL, EDSR(port));
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sh_eth_write(eth, EDSR_ENALL, EDSR);
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/* Perform a software reset and wait for it to complete */
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outl(EDMR_SRST, EDMR(port));
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sh_eth_write(eth, EDMR_SRST, EDMR);
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for (i = 0; i < TIMEOUT_CNT ; i++) {
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if (!(inl(EDMR(port)) & EDMR_SRST))
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if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
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break;
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udelay(1000);
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}
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@ -159,9 +158,9 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
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return ret;
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#else
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outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
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sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
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udelay(3000);
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outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
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sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
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return 0;
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#endif
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@ -207,11 +206,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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/* Point the controller to the tx descriptor list. Must use physical
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addresses */
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
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sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
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#if defined(SH_ETH_TYPE_GETHER)
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
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outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
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outl(0x01, TDFFR(port));/* Last discriptor bit */
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sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
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sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
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sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
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#endif
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err:
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@ -275,11 +274,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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cur_rx_desc->rd0 |= RD_RDLE;
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/* Point the controller to the rx descriptor list */
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
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sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
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#if defined(SH_ETH_TYPE_GETHER)
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
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outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
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outl(RDFFR_RDLF, RDFFR(port));
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sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
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sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
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sh_eth_write(eth, RDFFR_RDLF, RDFFR);
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#endif
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return ret;
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@ -364,38 +363,39 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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struct phy_device *phy;
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/* Configure e-dmac registers */
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outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
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outl(0, EESIPR(port));
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outl(0, TRSCER(port));
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outl(0, TFTR(port));
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outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
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outl(RMCR_RST, RMCR(port));
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sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
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EDMR);
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sh_eth_write(eth, 0, EESIPR);
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sh_eth_write(eth, 0, TRSCER);
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sh_eth_write(eth, 0, TFTR);
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sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
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sh_eth_write(eth, RMCR_RST, RMCR);
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#if defined(SH_ETH_TYPE_GETHER)
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outl(0, RPADIR(port));
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sh_eth_write(eth, 0, RPADIR);
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#endif
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outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
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sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
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/* Configure e-mac registers */
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outl(0, ECSIPR(port));
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sh_eth_write(eth, 0, ECSIPR);
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/* Set Mac address */
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val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
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dev->enetaddr[2] << 8 | dev->enetaddr[3];
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outl(val, MAHR(port));
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sh_eth_write(eth, val, MAHR);
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val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
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outl(val, MALR(port));
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sh_eth_write(eth, val, MALR);
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outl(RFLR_RFL_MIN, RFLR(port));
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sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
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#if defined(SH_ETH_TYPE_GETHER)
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outl(0, PIPR(port));
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outl(APR_AP, APR(port));
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outl(MPR_MP, MPR(port));
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outl(TPAUSER_TPAUSE, TPAUSER(port));
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sh_eth_write(eth, 0, PIPR);
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sh_eth_write(eth, APR_AP, APR);
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sh_eth_write(eth, MPR_MP, MPR);
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sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
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#endif
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#if defined(CONFIG_CPU_SH7734)
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outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
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sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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@ -416,34 +416,35 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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outl(GECMR_100B, GECMR(port));
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sh_eth_write(eth, GECMR_100B, GECMR);
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#elif defined(CONFIG_CPU_SH7757)
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outl(1, RTRATE(port));
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sh_eth_write(eth, 1, RTRATE);
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#elif defined(CONFIG_CPU_SH7724)
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val = ECMR_RTM;
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#endif
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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#if defined(SH_ETH_TYPE_GETHER)
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outl(GECMR_10B, GECMR(port));
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sh_eth_write(eth, GECMR_10B, GECMR);
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#elif defined(CONFIG_CPU_SH7757)
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outl(0, RTRATE(port));
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sh_eth_write(eth, 0, RTRATE);
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#endif
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}
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#if defined(SH_ETH_TYPE_GETHER)
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else if (phy->speed == 1000) {
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printf(SHETHER_NAME ": 1000Base/");
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outl(GECMR_1000B, GECMR(port));
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sh_eth_write(eth, GECMR_1000B, GECMR);
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex) {
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printf("Full\n");
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outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
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sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
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ECMR);
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} else {
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printf("Half\n");
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outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
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sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
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}
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return ret;
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@ -458,12 +459,12 @@ static void sh_eth_start(struct sh_eth_dev *eth)
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* Enable the e-dmac receiver only. The transmitter will be enabled when
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* we have something to transmit
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*/
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outl(EDRRR_R, EDRRR(eth->port));
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sh_eth_write(eth, EDRRR_R, EDRRR);
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}
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static void sh_eth_stop(struct sh_eth_dev *eth)
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{
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outl(~EDRRR_R, EDRRR(eth->port));
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sh_eth_write(eth, ~EDRRR_R, EDRRR);
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}
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int sh_eth_init(struct eth_device *dev, bd_t *bd)
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@ -567,9 +568,8 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
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static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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outl(inl(PIR(port)) | PIR_MMD, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
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return 0;
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}
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@ -577,9 +577,8 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
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static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
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return 0;
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}
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@ -587,12 +586,11 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
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static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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if (v)
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outl(inl(PIR(port)) | PIR_MDO, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
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else
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outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
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return 0;
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}
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@ -600,9 +598,8 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
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static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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*v = (inl(PIR(port)) & PIR_MDI) >> 3;
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*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
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return 0;
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}
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@ -610,12 +607,11 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
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static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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if (v)
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outl(inl(PIR(port)) | PIR_MDC, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
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else
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outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
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sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
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return 0;
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}
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@ -97,140 +97,196 @@ struct sh_eth_dev {
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struct sh_eth_info port_info[MAX_PORT_NUM];
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};
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/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
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enum {
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/* E-DMAC registers */
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EDSR = 0,
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EDMR,
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EDTRR,
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EDRRR,
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EESR,
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EESIPR,
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TDLAR,
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TDFAR,
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TDFXR,
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TDFFR,
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RDLAR,
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RDFAR,
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RDFXR,
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RDFFR,
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TRSCER,
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RMFCR,
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TFTR,
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FDR,
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RMCR,
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EDOCR,
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TFUCR,
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RFOCR,
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FCFTR,
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RPADIR,
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TRIMD,
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RBWAR,
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TBRAR,
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/* Ether registers */
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ECMR,
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ECSR,
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ECSIPR,
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PIR,
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PSR,
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RDMLR,
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PIPR,
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RFLR,
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IPGR,
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APR,
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MPR,
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PFTCR,
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PFRCR,
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RFCR,
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RFCF,
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TPAUSER,
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TPAUSECR,
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BCFR,
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BCFRR,
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GECMR,
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BCULR,
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MAHR,
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MALR,
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TROCR,
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CDCR,
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LCCR,
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CNDCR,
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CEFCR,
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FRECR,
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TSFRCR,
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TLFRCR,
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CERCR,
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CEECR,
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MAFCR,
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RTRATE,
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CSMR,
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RMII_MII,
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/* This value must be written at last. */
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SH_ETH_MAX_REGISTER_OFFSET,
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};
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[RMII_MII] = 0x0790,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
|
||||
[TPAUSECR] = 0x0168,
|
||||
[BCFRR] = 0x016c,
|
||||
[MAHR] = 0x01c0,
|
||||
[MALR] = 0x01c8,
|
||||
[TROCR] = 0x01d0,
|
||||
[CDCR] = 0x01d4,
|
||||
[LCCR] = 0x01d8,
|
||||
[CNDCR] = 0x01dc,
|
||||
[CEFCR] = 0x01e4,
|
||||
[FRECR] = 0x01e8,
|
||||
[TSFRCR] = 0x01ec,
|
||||
[TLFRCR] = 0x01f0,
|
||||
[RFCR] = 0x01f4,
|
||||
[MAFCR] = 0x01f8,
|
||||
[RTRATE] = 0x01fc,
|
||||
|
||||
[EDMR] = 0x0000,
|
||||
[EDTRR] = 0x0008,
|
||||
[EDRRR] = 0x0010,
|
||||
[TDLAR] = 0x0018,
|
||||
[RDLAR] = 0x0020,
|
||||
[EESR] = 0x0028,
|
||||
[EESIPR] = 0x0030,
|
||||
[TRSCER] = 0x0038,
|
||||
[RMFCR] = 0x0040,
|
||||
[TFTR] = 0x0048,
|
||||
[FDR] = 0x0050,
|
||||
[RMCR] = 0x0058,
|
||||
[TFUCR] = 0x0064,
|
||||
[RFOCR] = 0x0068,
|
||||
[FCFTR] = 0x0070,
|
||||
[RPADIR] = 0x0078,
|
||||
[TRIMD] = 0x007c,
|
||||
[RBWAR] = 0x00c8,
|
||||
[RDFAR] = 0x00cc,
|
||||
[TBRAR] = 0x00d4,
|
||||
[TDFAR] = 0x00d8,
|
||||
};
|
||||
|
||||
/* Register Address */
|
||||
#ifdef CONFIG_CPU_SH7763
|
||||
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
|
||||
#define SH_ETH_TYPE_GETHER
|
||||
#define BASE_IO_ADDR 0xfee00000
|
||||
|
||||
#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
|
||||
|
||||
#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
|
||||
#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
|
||||
#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
|
||||
#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
|
||||
|
||||
#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
|
||||
#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
|
||||
#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
|
||||
#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
|
||||
|
||||
#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
|
||||
#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
|
||||
#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
|
||||
#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
|
||||
#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
|
||||
#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
|
||||
#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
|
||||
#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
|
||||
#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
|
||||
#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
|
||||
#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
|
||||
#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
|
||||
#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
|
||||
#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
|
||||
#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
|
||||
#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
|
||||
#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
|
||||
#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
|
||||
#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
|
||||
#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
|
||||
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
|
||||
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
|
||||
|
||||
#elif defined(CONFIG_CPU_SH7757)
|
||||
#define SH_ETH_TYPE_ETHER
|
||||
#define BASE_IO_ADDR 0xfef00000
|
||||
|
||||
#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
|
||||
#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
|
||||
|
||||
#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
|
||||
#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
|
||||
#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
|
||||
#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
|
||||
#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
|
||||
#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
|
||||
#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
|
||||
#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
|
||||
#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
|
||||
#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
|
||||
#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
|
||||
#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
|
||||
#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
|
||||
#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
|
||||
#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
|
||||
#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
|
||||
#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
|
||||
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
|
||||
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
|
||||
#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
|
||||
|
||||
#elif defined(CONFIG_CPU_SH7724)
|
||||
#define SH_ETH_TYPE_ETHER
|
||||
#define BASE_IO_ADDR 0xA4600000
|
||||
|
||||
#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
|
||||
#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
|
||||
|
||||
#define EDMR(port) (BASE_IO_ADDR + 0x0000)
|
||||
#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
|
||||
#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
|
||||
#define EESR(port) (BASE_IO_ADDR + 0x0028)
|
||||
#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
|
||||
#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
|
||||
#define TFTR(port) (BASE_IO_ADDR + 0x0048)
|
||||
#define FDR(port) (BASE_IO_ADDR + 0x0050)
|
||||
#define RMCR(port) (BASE_IO_ADDR + 0x0058)
|
||||
#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
|
||||
#define ECMR(port) (BASE_IO_ADDR + 0x0100)
|
||||
#define RFLR(port) (BASE_IO_ADDR + 0x0108)
|
||||
#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
|
||||
#define PIR(port) (BASE_IO_ADDR + 0x0120)
|
||||
#define APR(port) (BASE_IO_ADDR + 0x0154)
|
||||
#define MPR(port) (BASE_IO_ADDR + 0x0158)
|
||||
#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
|
||||
#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
|
||||
#define MALR(port) (BASE_IO_ADDR + 0x01c8)
|
||||
|
||||
#elif defined(CONFIG_CPU_SH7734)
|
||||
#define SH_ETH_TYPE_GETHER
|
||||
#define BASE_IO_ADDR 0xFEE00000
|
||||
|
||||
#define EDSR(port) (BASE_IO_ADDR)
|
||||
|
||||
#define TDLAR(port) (BASE_IO_ADDR + 0x0010)
|
||||
#define TDFAR(port) (BASE_IO_ADDR + 0x0014)
|
||||
#define TDFXR(port) (BASE_IO_ADDR + 0x0018)
|
||||
#define TDFFR(port) (BASE_IO_ADDR + 0x001c)
|
||||
#define RDLAR(port) (BASE_IO_ADDR + 0x0030)
|
||||
#define RDFAR(port) (BASE_IO_ADDR + 0x0034)
|
||||
#define RDFXR(port) (BASE_IO_ADDR + 0x0038)
|
||||
#define RDFFR(port) (BASE_IO_ADDR + 0x003c)
|
||||
|
||||
#define EDMR(port) (BASE_IO_ADDR + 0x0400)
|
||||
#define EDTRR(port) (BASE_IO_ADDR + 0x0408)
|
||||
#define EDRRR(port) (BASE_IO_ADDR + 0x0410)
|
||||
#define EESR(port) (BASE_IO_ADDR + 0x0428)
|
||||
#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
|
||||
#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
|
||||
#define TFTR(port) (BASE_IO_ADDR + 0x0448)
|
||||
#define FDR(port) (BASE_IO_ADDR + 0x0450)
|
||||
#define RMCR(port) (BASE_IO_ADDR + 0x0458)
|
||||
#define RPADIR(port) (BASE_IO_ADDR + 0x0460)
|
||||
#define FCFTR(port) (BASE_IO_ADDR + 0x0468)
|
||||
#define ECMR(port) (BASE_IO_ADDR + 0x0500)
|
||||
#define RFLR(port) (BASE_IO_ADDR + 0x0508)
|
||||
#define ECSIPR(port) (BASE_IO_ADDR + 0x0518)
|
||||
#define PIR(port) (BASE_IO_ADDR + 0x0520)
|
||||
#define PIPR(port) (BASE_IO_ADDR + 0x052c)
|
||||
#define APR(port) (BASE_IO_ADDR + 0x0554)
|
||||
#define MPR(port) (BASE_IO_ADDR + 0x0558)
|
||||
#define TPAUSER(port) (BASE_IO_ADDR + 0x0564)
|
||||
#define GECMR(port) (BASE_IO_ADDR + 0x05b0)
|
||||
#define MAHR(port) (BASE_IO_ADDR + 0x05C0)
|
||||
#define MALR(port) (BASE_IO_ADDR + 0x05C8)
|
||||
#define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -506,3 +562,28 @@ enum RPADIR_BIT {
|
||||
enum FIFO_SIZE_BIT {
|
||||
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
|
||||
};
|
||||
|
||||
static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
|
||||
int enum_index)
|
||||
{
|
||||
#if defined(SH_ETH_TYPE_GETHER)
|
||||
const u16 *reg_offset = sh_eth_offset_gigabit;
|
||||
#elif defined(SH_ETH_TYPE_ETHER)
|
||||
const u16 *reg_offset = sh_eth_offset_fast_sh4;
|
||||
#else
|
||||
#error
|
||||
#endif
|
||||
return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
|
||||
}
|
||||
|
||||
static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
|
||||
int enum_index)
|
||||
{
|
||||
outl(data, sh_eth_reg_addr(eth, enum_index));
|
||||
}
|
||||
|
||||
static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
|
||||
int enum_index)
|
||||
{
|
||||
return inl(sh_eth_reg_addr(eth, enum_index));
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user