Merge branch 'master' of /home/wd/git/u-boot/custodians

This commit is contained in:
Wolfgang Denk 2010-11-30 22:13:32 +01:00
commit 49733aa0b9
17 changed files with 66 additions and 20 deletions

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@ -48,10 +48,11 @@ u32 is_mem_sdr(void)
*/
u32 get_sdr_cs_size(u32 cs)
{
u32 size;
u32 size = 0;
/* TODO: Calculate the size based on EMIF4 configuration */
size = CONFIG_SYS_CS0_SIZE;
if (cs == CS0)
size = CONFIG_SYS_CS0_SIZE;
return size;
}

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@ -65,15 +65,12 @@ int timer_init(void)
writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
if (count_value == 0) {
/* reset initial value */
/* count_value = 2085937.5(HZ) (per 1 sec)*/
count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
(MUX_DIV_2 + 1));
/* count_value = 2085937.5(HZ) (per 1 sec)*/
count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
(MUX_DIV_2 + 1));
/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
count_value = count_value / 100;
}
/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
count_value = count_value / 100;
/* set count value */
writel(count_value, &timer->tcntb4);
@ -114,8 +111,11 @@ void set_timer(unsigned long t)
/* delay x useconds */
void __udelay(unsigned long usec)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long tmo, tmp;
count_value = readl(&timer->tcntb4);
if (usec >= 1000) {
/*
* if "big" number, spread normalization

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@ -27,4 +27,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

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@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

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@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

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@ -42,6 +42,14 @@ int board_init(void)
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
PHYS_SDRAM_3_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@ -49,8 +57,6 @@ int dram_init(void)
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO

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@ -65,13 +65,17 @@ int board_init(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{

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@ -30,4 +30,4 @@
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80e80000
CONFIG_SYS_TEXT_BASE = 0x80008000

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@ -163,6 +163,7 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
@ -330,4 +331,10 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -110,6 +110,7 @@
#define CONFIG_MTD_DEVICE
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* nfs */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_IMLS /* List all found images */

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@ -330,7 +330,11 @@ extern unsigned int boot_flash_type;
* Support for relocation
*/
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Define the board revision statically

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@ -309,6 +309,12 @@
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* SDRAM Memory Map
*/

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@ -236,6 +236,12 @@
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).

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@ -188,6 +188,12 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Miscellaneous configurable options
*/

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@ -139,6 +139,7 @@
/* Disabled commands */
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */

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@ -217,4 +217,6 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#endif /* __CONFIG_H */

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@ -231,6 +231,8 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
/*
* Ethernet Contoller driver
*/