x86: quark: Add platform ASL files
This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
parent
ec37913221
commit
48cf8b8346
15
arch/x86/include/asm/arch-quark/acpi/irqroute.h
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15
arch/x86/include/asm/arch-quark/acpi/irqroute.h
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@ -0,0 +1,15 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/device.h>
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
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125
arch/x86/include/asm/arch-quark/acpi/lpc.asl
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125
arch/x86/include/asm/arch-quark/acpi/lpc.asl
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@ -0,0 +1,125 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Intel LPC Bus Device - 0:1f.0 */
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Device (LPCB)
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{
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Name(_ADR, 0x001f0000)
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OperationRegion(PRTX, PCI_Config, 0x60, 8)
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Field(PRTX, AnyAcc, NoLock, Preserve) {
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PRTA, 8,
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PRTB, 8,
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PRTC, 8,
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PRTD, 8,
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PRTE, 8,
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PRTF, 8,
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PRTG, 8,
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PRTH, 8,
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}
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#include <asm/acpi/irqlinks.asl>
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/* Firmware Hub */
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Device (FWH)
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{
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Name(_HID, EISAID("INT0800"))
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
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})
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}
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/* 8259 Interrupt Controller */
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Device (PIC)
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{
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Name(_HID, EISAID("PNP0000"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x20, 0x20, 0x01, 0x02)
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IO(Decode16, 0x24, 0x24, 0x01, 0x02)
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IO(Decode16, 0x28, 0x28, 0x01, 0x02)
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IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO(Decode16, 0x30, 0x30, 0x01, 0x02)
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IO(Decode16, 0x34, 0x34, 0x01, 0x02)
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IO(Decode16, 0x38, 0x38, 0x01, 0x02)
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IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO(Decode16, 0xac, 0xac, 0x01, 0x02)
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IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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/* 8254 timer */
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Device (TIMR)
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{
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Name(_HID, EISAID("PNP0100"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x40, 0x40, 0x01, 0x04)
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IO(Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags() { 0 }
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})
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}
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/* HPET */
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Device (HPET)
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{
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Name(_HID, EISAID("PNP0103"))
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Name(_CID, 0x010CD041)
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
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})
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* Real Time Clock */
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Device (RTC)
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{
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Name(_HID, EISAID("PNP0B00"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x70, 0x70, 1, 8)
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IRQNoFlags() { 8 }
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})
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}
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/* LPC device: Resource consumption */
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Device (LDRC)
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{
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Name(_HID, EISAID("PNP0C02"))
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Name(_UID, 2)
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Name(RBUF, ResourceTemplate()
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{
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IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
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IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
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IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
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})
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Method(_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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}
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}
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33
arch/x86/include/asm/arch-quark/acpi/platform.asl
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33
arch/x86/include/asm/arch-quark/acpi/platform.asl
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@ -0,0 +1,33 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/acpi/statdef.asl>
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#include <asm/arch/iomap.h>
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#include <asm/arch/irq.h>
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0.
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*/
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Method(_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK, 1)
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{
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Return (Package() {0, 0})
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}
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/* TODO: add CPU ASL support */
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Scope (\_SB)
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{
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#include "southcluster.asl"
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}
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/* Chipset specific sleep states */
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#include "sleepstates.asl"
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10
arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
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10
arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
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@ -0,0 +1,10 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
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Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
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Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
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Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
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184
arch/x86/include/asm/arch-quark/acpi/southcluster.asl
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184
arch/x86/include/asm/arch-quark/acpi/southcluster.asl
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@ -0,0 +1,184 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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Device (PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) /* PCIe */
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Name(_CID, EISAID("PNP0A03")) /* PCI */
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Name(_ADR, 0)
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Name(_BBN, 0)
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Name(MCRS, ResourceTemplate()
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{
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/* Bus Numbers */
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
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/* IO Region 0 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
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/* PCI Config Space */
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IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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/* IO Region 1 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
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/* VGA memory (0xa0000-0xbffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000, , , ASEG)
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/* OPROM reserved (0xc0000-0xc3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000, , , OPR0)
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/* OPROM reserved (0xc4000-0xc7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000, , , OPR1)
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/* OPROM reserved (0xc8000-0xcbfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000, , , OPR2)
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/* OPROM reserved (0xcc000-0xcffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000, , , OPR3)
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/* OPROM reserved (0xd0000-0xd3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000, , , OPR4)
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/* OPROM reserved (0xd4000-0xd7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000, , , OPR5)
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/* OPROM reserved (0xd8000-0xdbfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000, , , OPR6)
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/* OPROM reserved (0xdc000-0xdffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000, , , OPR7)
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/* BIOS Extension (0xe0000-0xe3fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000, , , ESG0)
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/* BIOS Extension (0xe4000-0xe7fff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000, , , ESG1)
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/* BIOS Extension (0xe8000-0xebfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000, , , ESG2)
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/* BIOS Extension (0xec000-0xeffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000, , , ESG3)
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/* System BIOS (0xf0000-0xfffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000, , , FSEG)
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/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, , , PMEM)
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})
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Method(_CRS, 0, Serialized)
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{
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/* Update PCI resource area */
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CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
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CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
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CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
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/*
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* Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
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*
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* TODO: for generic usage, read TOLM value from register, or
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* from global NVS (not implemented by U-Boot yet).
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*/
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Store(0x80000000, PMIN)
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Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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Return (MCRS)
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}
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/* Device Resource Consumption */
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Device (PDRC)
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{
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Name(_HID, EISAID("PNP0C02"))
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Name(_UID, 1)
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Name(PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
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Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
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IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
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IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
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})
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/* Current Resource Settings */
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Method(_CRS, 0, Serialized)
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{
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Return (PDRS)
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}
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}
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Method(_OSC, 4)
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{
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/* Check for proper GUID */
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If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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/* Unrecognized UUID */
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CreateDWordField(Arg3, 0, CDW1)
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Or(CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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/* LPC Bridge 0:1f.0 */
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#include "lpc.asl"
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/* IRQ routing for each PCI device */
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#include <asm/acpi/irqroute.asl>
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}
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47
arch/x86/include/asm/arch-quark/iomap.h
Normal file
47
arch/x86/include/asm/arch-quark/iomap.h
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/*
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUARK_IOMAP_H_
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#define _QUARK_IOMAP_H_
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/* Memory Mapped IO bases */
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/* ESRAM */
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#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
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#define ESRAM_BASE_SIZE ESRAM_SIZE
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/* PCI Configuration Space */
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#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
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#define MCFG_BASE_SIZE 0x10000000
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/* High Performance Event Timer */
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#define HPET_BASE_ADDRESS 0xfed00000
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#define HPET_BASE_SIZE 0x400
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/* Root Complex Base Address */
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#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
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#define RCBA_BASE_SIZE 0x4000
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/* IO Port bases */
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#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
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#define ACPI_PM1_BASE_SIZE 0x10
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#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
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#define ACPI_PBLK_BASE_SIZE 0x10
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#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
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#define SPI_DMA_BASE_SIZE 0x10
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#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
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#define GPIO_BASE_SIZE 0x80
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#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
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#define ACPI_GPE0_BASE_SIZE 0x40
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#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
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#define WDT_BASE_SIZE 0x40
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#endif /* _QUARK_IOMAP_H_ */
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19
arch/x86/include/asm/arch-quark/irq.h
Normal file
19
arch/x86/include/asm/arch-quark/irq.h
Normal file
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/*
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUARK_IRQ_H_
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#define _QUARK_IRQ_H_
|
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#define PIRQA_APIC_IRQ 16
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#define PIRQB_APIC_IRQ 17
|
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#define PIRQC_APIC_IRQ 18
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#define PIRQD_APIC_IRQ 19
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#define PIRQE_APIC_IRQ 20
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#define PIRQF_APIC_IRQ 21
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#define PIRQG_APIC_IRQ 22
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#define PIRQH_APIC_IRQ 23
|
||||
|
||||
#endif /* _QUARK_IRQ_H_ */
|
||||
Loading…
Reference in New Issue
Block a user