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MIPS: Allow to prefetch and lock instructions into cache

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This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Gregory CLEMENT 2018-12-14 16:16:46 +01:00 committed by Daniel Schwierzeck
parent 48ee7b6853
commit 464b96bb80
1 changed files with 19 additions and 0 deletions
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19
arch/mips/include/asm/cacheops.h
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@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr)
#endif
}
#define MIPS32_WHICH_ICACHE 0x0
#define MIPS32_FETCH_AND_LOCK 0x7
#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
/* Prefetch and lock instructions into cache */
static inline void icache_lock(void *func, size_t len)
{
int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
for (i = 0; i < lines; i++) {
asm volatile (" cache %0, %1(%2)"
: /* No Output */
: "I" ICACHE_LOAD_LOCK,
"n" (i * ARCH_DMA_MINALIGN),
"r" (func)
: /* No Clobbers */);
}
}
#endif /* !__ASSEMBLY__ */
/*