85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
c8c41d4a80
commit
44a23cfd63
@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a
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START = start.o resetvec.o
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COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
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pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
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$(COBJS-y)
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@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
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ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
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while (ram_tlb_address < (memsize * 1024 * 1024)
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&& ram_tlb_index < 16) {
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mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
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mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
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mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
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mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR)));
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asm volatile("isync;msync;tlbwe;isync");
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debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
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debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
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debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
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debug("DDR: MAS3=0x%08x\n",
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FSL_BOOKE_MAS3(ram_tlb_address, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR)));
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set_tlb(1, ram_tlb_address, ram_tlb_address,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, ram_tlb_index, tlb_size, 1);
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ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
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ram_tlb_index++;
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95
cpu/mpc85xx/tlb.c
Normal file
95
cpu/mpc85xx/tlb.c
Normal file
@ -0,0 +1,95 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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void set_tlb(u8 tlb, u32 epn, u64 rpn,
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u8 perms, u8 wimge,
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u8 ts, u8 esel, u8 tsize, u8 iprot)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
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_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
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_mas2 = FSL_BOOKE_MAS2(epn, wimge);
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_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
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_mas7 = rpn >> 32;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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}
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void disable_tlb(u8 esel)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
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_mas1 = 0;
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_mas2 = 0;
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_mas3 = 0;
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_mas7 = 0;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, _mas7);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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}
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void invalidate_tlb(u8 tlb)
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{
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if (tlb == 0)
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mtspr(MMUCSR0, 0x4);
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if (tlb == 1)
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mtspr(MMUCSR0, 0x2);
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}
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void init_tlbs(void)
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{
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#ifdef CONFIG_FSL_INIT_TLBS
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
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tlb_table[i].perms, tlb_table[i].wimge,
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tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
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tlb_table[i].iprot);
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}
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#endif
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return ;
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}
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@ -418,6 +418,37 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
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#define BOOKE_PAGESZ_256GB 14
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#define BOOKE_PAGESZ_1TB 15
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#ifdef CONFIG_E500
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#ifndef __ASSEMBLY__
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extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
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u8 perms, u8 wimge,
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u8 ts, u8 esel, u8 tsize, u8 iprot);
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extern void disable_tlb(u8 esel);
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extern void invalidate_tlb(u8 tlb);
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extern void init_tlbs(void);
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
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{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
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.wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
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struct fsl_e_tlb_entry {
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u8 tlb;
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u32 epn;
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u64 rpn;
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u8 perms;
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u8 wimge;
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u8 ts;
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u8 esel;
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u8 tsize;
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u8 iprot;
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};
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extern struct fsl_e_tlb_entry tlb_table[];
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extern int num_tlb_entries;
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#endif
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#endif
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#if defined(CONFIG_MPC86xx)
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#define LAWBAR_BASE_ADDR 0x00FFFFFF
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#define LAWAR_TRGT_IF 0x01F00000
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