armv8: LS2080A: Rename LS2085A to reflect LS2080A

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-09 16:42:07 +05:30 · 2015-11-09 16:42:07 +05:30 · 449372148f
commit 449372148f
parent 14480454c7
67 changed files with 251 additions and 197 deletions
--- a/3
+++ b/3
@ -611,6 +611,9 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 		Number of controllers used for other than main memory.

+		CONFIG_SYS_FSL_HAS_DP_DDR
+		Defines the SoC has DP-DDR used for DPAA.
+
 		CONFIG_SYS_FSL_SEC_BE
 		Defines the SEC controller register space as Big Endian

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -589,36 +589,46 @@ config TARGET_VEXPRESS64_JUNO
 	bool "Support Versatile Express Juno Development Platform"
 	select ARM64

-config TARGET_LS2085A_EMU
-	bool "Support ls2085a_emu"
+config TARGET_LS2080A_EMU
+	bool "Support ls2080a_emu"
 	select ARM64
 	select ARMV8_MULTIENTRY
-
-config TARGET_LS2085A_SIMU
-	bool "Support ls2085a_simu"
-	select ARM64
-	select ARMV8_MULTIENTRY
-
-config TARGET_LS2085AQDS
-	bool "Support ls2085aqds"
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
 	help
-	  Support for Freescale LS2085AQDS platform
-	  The LS2085A Development System (QDS) is a high-performance
-	  development platform that supports the QorIQ LS2085A
+	  Support for Freescale LS2080A_EMU platform
+	  The LS2080A Development System (EMULATOR) is a pre silicon
+	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.

-config TARGET_LS2085ARDB
-	bool "Support ls2085ardb"
+config TARGET_LS2080A_SIMU
+	bool "Support ls2080a_simu"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS2080A_SIMU platform
+	  The LS2080A Development System (QDS) is a pre silicon
+	  development platform that supports the QorIQ LS2080A
+	  Layerscape Architecture processor.
+
+config TARGET_LS2080AQDS
+	bool "Support ls2080aqds"
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
 	help
-	  Support for Freescale LS2085ARDB platform.
-	  The LS2085A Reference design board (RDB) is a high-performance
-	  development platform that supports the QorIQ LS2085A
+	  Support for Freescale LS2080AQDS platform
+	  The LS2080A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS2080A
+	  Layerscape Architecture processor.
+
+config TARGET_LS2080ARDB
+	bool "Support ls2080ardb"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	help
+	  Support for Freescale LS2080ARDB platform.
+	  The LS2080A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.

 config TARGET_HIKEY
@ -759,9 +769,9 @@ source "board/compulab/cm_t43/Kconfig"
 source "board/creative/xfi3/Kconfig"
 source "board/denx/m28evk/Kconfig"
 source "board/denx/m53evk/Kconfig"
-source "board/freescale/ls2085a/Kconfig"
-source "board/freescale/ls2085aqds/Kconfig"
-source "board/freescale/ls2085ardb/Kconfig"
+source "board/freescale/ls2080a/Kconfig"
+source "board/freescale/ls2080aqds/Kconfig"
+source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@ -21,8 +21,8 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
 endif
 endif

-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+ifneq ($(CONFIG_LS2080A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 else
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@ -7,7 +7,7 @@
 Freescale LayerScape with Chassis Generation 3

 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2085A.
+for example LS2080A.

 DDR Layout
 ============
@ -152,7 +152,7 @@ u-boot command
 nand write <rcw image in memory> 0 <size of rcw image>

 To form the NAND image, build u-boot with NAND config, for example,
-ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.

 nand write <u-boot image in memory> 200000 <size of u-boot image>
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@ -438,7 +438,7 @@ int print_cpuinfo(void)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
 #endif
 	puts("\n");
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@ -141,7 +141,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,

 /*
 * The info below summarizes how streamID partitioning works
- * for ls2085a and how it is conveyed to the OS via the device tree.
+ * for ls2080a and how it is conveyed to the OS via the device tree.
 *
 *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
 *     -all legacy devices get a unique ICID assigned and programmed in
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@ -11,6 +11,7 @@
 #include <fsl_ifc.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/soc.h>
 #include "cpu.h"
@ -77,10 +78,14 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_systembus = sysclk;
 #ifdef CONFIG_DDR_CLK_FREQ
 	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+#endif
 #else
 	sys_info->freq_ddrbus = sysclk;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 = sysclk;
+#endif
 #endif

 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
@ -91,9 +96,11 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+#endif

 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		/*
@ -133,7 +140,9 @@ int get_clocks(void)
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus;
 	gd->mem_clk = sys_info.freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	gd->arch.mem2_clk = sys_info.freq_ddrbus2;
+#endif
 #if defined(CONFIG_FSL_ESDHC)
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif /* defined(CONFIG_FSL_ESDHC) */
@ -169,8 +178,10 @@ ulong get_ddr_freq(ulong ctrl_num)
 	 * DDR controller 0 & 1 are on memory complex 0
 	 * DDR controler 2 is on memory complext 1
 	 */
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num >= 2)
 		return gd->arch.mem2_clk;
+#endif

 	return gd->mem_clk;
 }
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@ -12,7 +12,7 @@

 DECLARE_GLOBAL_DATA_PTR;

-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 static void erratum_a008751(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@ -48,7 +48,7 @@ void board_init_f(ulong dummy)
 	gd = &gdata;
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	arch_cpu_init();
 #endif
 #ifdef CONFIG_FSL_IFC
@ -56,7 +56,7 @@ void board_init_f(ulong dummy)
 #endif
 	board_early_init_f();
 	timer_init();
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	env_init();
 #endif
 	get_clocks();
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@ -87,8 +87,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb

 dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 	ls1021a-twr.dtb
-dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
-	fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+	fsl-ls2080a-rdb.dtb

 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a QDS board device tree source
+ * Freescale ls2080a QDS board device tree source
 *
 * Copyright 2013-2015 Freescale Semiconductor, Inc.
 *
@ -8,11 +8,11 @@

 /dts-v1/;

-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"

 / {
-	model = "Freescale Layerscape 2085a QDS Board";
-	compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+	model = "Freescale Layerscape 2080a QDS Board";
+	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";

 	aliases {
 		spi1 = &dspi;
--- a/arch/arm/dts/fsl-ls2080a-rdb.dts
+++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a RDB board device tree source
+ * Freescale ls2080a RDB board device tree source
 *
 * Copyright 2013-2015 Freescale Semiconductor, Inc.
 *
@ -8,11 +8,11 @@

 /dts-v1/;

-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"

 / {
-	model = "Freescale Layerscape 2085a RDB Board";
-	compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+	model = "Freescale Layerscape 2080a RDB Board";
+	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";

 	aliases {
 		spi1 = &dspi;
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@ -1,5 +1,5 @@
 /*
- * Freescale ls2085a SOC common device tree source
+ * Freescale ls2080a SOC common device tree source
 *
 * Copyright 2013-2015 Freescale Semiconductor, Inc.
 *
@ -7,7 +7,7 @@
 */

 / {
-	compatible = "fsl,ls2085a";
+	compatible = "fsl,ls2080a";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@ -17,10 +17,10 @@
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0

-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A)
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		3
+#define CONFIG_NUM_DDR_CONTROLLERS		2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_FSL_SRDS_1
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@ -8,8 +8,8 @@
 #define _FSL_LAYERSCAPE_CPU_H

 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 };
@ -180,7 +180,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 #endif
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@ -9,7 +9,7 @@

 #include <config.h>

-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@ -51,8 +51,8 @@
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)

-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)

 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
@ -115,7 +115,9 @@ struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	unsigned long freq_ddrbus2;
+#endif
 	unsigned long freq_localbus;
 	unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN
--- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
@ -7,7 +7,7 @@
 #ifndef __FSL_STREAM_ID_H
 #define __FSL_STREAM_ID_H

-/* Stream IDs on ls2085a devices are not hardwired and are
+/* Stream IDs on ls2080a devices are not hardwired and are
 * programmed by sw.  There are a limited number of stream IDs
 * available, and the partitioning of them is scenario dependent.
 * This header defines the partitioning between legacy, PCI,
@ -17,7 +17,7 @@
 * on the specific hardware config-- e.g. perhaps not all
 * PEX controllers are in use.
 *
- * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
+ * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
 * each of the different bus masters.  The relationship between
 * the AMQ registers and stream IDs is defined in the table below:
 *          AMQ bit    streamID bit
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@ -46,7 +46,7 @@ struct arch_global_data {
 	u32 omap_boot_mode;
 	u8 omap_ch_flags;
 #endif
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
 	unsigned long mem2_clk;
 #endif
 };
--- a/board/freescale/ls2080a/Kconfig
+++ b/board/freescale/ls2080a/Kconfig
@ -1,7 +1,7 @@
-if TARGET_LS2085A_EMU
+if TARGET_LS2080A_EMU

 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"

 config SYS_VENDOR
 	default "freescale"
@ -10,14 +10,14 @@ config SYS_SOC
 	default "fsl-layerscape"

 config SYS_CONFIG_NAME
-	default "ls2085a_emu"
+	default "ls2080a_emu"

 endif

-if TARGET_LS2085A_SIMU
+if TARGET_LS2080A_SIMU

 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"

 config SYS_VENDOR
 	default "freescale"
@ -26,6 +26,6 @@ config SYS_SOC
 	default "fsl-layerscape"

 config SYS_CONFIG_NAME
-	default "ls2085a_simu"
+	default "ls2080a_simu"

 endif
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	York Sun <yorksun@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080a/
+F:	include/configs/ls2080a_emu.h
+F:	configs/ls2080a_emu_defconfig
+F:	include/configs/ls2080a_simu.h
+F:	configs/ls2080a_simu_defconfig
--- a/board/freescale/ls2080a/Makefile
+++ b/board/freescale/ls2080a/Makefile
@ -0,0 +1,8 @@
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o
--- a/board/freescale/ls2080a/README
+++ b/board/freescale/ls2080a/README
@ -1,4 +1,4 @@
-Freescale ls2085a_emu
+Freescale ls2080a_emu

 This is a emulator target with limited peripherals.

--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@ -71,7 +71,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@ -79,6 +79,7 @@ found:
 		popts->burst_length = DDR_BL8;
 		popts->bstopre = 0;	/* enable auto precharge */
 	}
+#endif
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
--- a/board/freescale/ls2080a/ddr.h
+++ b/board/freescale/ls2080a/ddr.h
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@ -41,11 +41,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }

 int dram_init(void)
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@ -1,8 +1,8 @@

-if TARGET_LS2085ARDB
+if TARGET_LS2080AQDS

 config SYS_BOARD
-	default "ls2085ardb"
+	default "ls2080aqds"

 config SYS_VENDOR
 	default "freescale"
@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"

 config SYS_CONFIG_NAME
-	default "ls2085ardb"
+	default "ls2080aqds"

 endif
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080aqds/
+F:	board/freescale/ls2080a/ls2080aqds.c
+F:	include/configs/ls2080aqds.h
+F:	configs/ls2080aqds_defconfig
+F:	configs/ls2080aqds_nand_defconfig
--- a/board/freescale/ls2080aqds/Makefile
+++ b/board/freescale/ls2080aqds/Makefile
@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #

-obj-y += ls2085aqds.o
+obj-y += ls2080aqds.o
 obj-y += ddr.o
 obj-y += eth.o
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@ -1,19 +1,19 @@
 Overview
 --------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.

-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.

-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:

 - Eight 64-bit ARM Cortex-A57 CPUs
 - 1 MB platform cache with ECC
@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features:
 - Service processor (SP) provides pre-boot initialization and secure-boot
  capabilities

- LS2085AQDS board Overview
+ LS2080AQDS board Overview
 -----------------------
 - SERDES Connections, 16 lanes supporting:
      - PCI Express - 3.0
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;
@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@ -18,16 +18,16 @@

 #include "../common/qixis.h"

-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"


 #ifdef CONFIG_FSL_MC_ENET
- /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
 *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
 *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
 */

- /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
  * means that the mapping must be determined dynamically, or that the lane
  * maps to something other than a board slot.
  */
@ -74,16 +74,16 @@ static int sgmii_riser_phy_addr[] = {
 #define SFP_TX		0

 static const char * const mdio_names[] = {
-	"LS2085A_QDS_MDIO0",
-	"LS2085A_QDS_MDIO1",
-	"LS2085A_QDS_MDIO2",
-	"LS2085A_QDS_MDIO3",
-	"LS2085A_QDS_MDIO4",
-	"LS2085A_QDS_MDIO5",
+	"LS2080A_QDS_MDIO0",
+	"LS2080A_QDS_MDIO1",
+	"LS2080A_QDS_MDIO2",
+	"LS2080A_QDS_MDIO3",
+	"LS2080A_QDS_MDIO4",
+	"LS2080A_QDS_MDIO5",
 	DEFAULT_WRIOP_MDIO2_NAME,
 };

-struct ls2085a_qds_mdio {
+struct ls2080a_qds_mdio {
 	u8 muxval;
 	struct mii_dev *realbus;
 };
@ -95,7 +95,7 @@ static void sgmii_configure_repeater(int serdes_port)
 	int i, j, ret;
 	int dpmac_id = 0, dpmac, mii_bus = 0;
 	unsigned short value;
-	char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
+	char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
 	uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};

 	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
@ -222,7 +222,7 @@ static void qsgmii_configure_repeater(int dpmac)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

-	const char *dev = "LS2085A_QDS_MDIO0";
+	const char *dev = "LS2080A_QDS_MDIO0";
 	int ret = 0;
 	unsigned short value;

@ -318,7 +318,7 @@ error:
 	return;
 }

-static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
 {
 	return mdio_names[muxval];
 }
@ -326,7 +326,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 {
 	struct mii_dev *bus;
-	const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+	const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);

 	if (!name) {
 		printf("No bus for muxval %x\n", muxval);
@ -343,7 +343,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval)
 	return bus;
 }

-static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
 {
 	u8 brdcfg9;

@ -353,7 +353,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval)
 	QIXIS_WRITE(brdcfg[9], brdcfg9);
 }

-static void ls2085a_qds_mux_mdio(u8 muxval)
+static void ls2080a_qds_mux_mdio(u8 muxval)
 {
 	u8 brdcfg4;

@ -365,54 +365,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval)
 	}
 }

-static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
 				 int devad, int regnum)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;

-	ls2085a_qds_mux_mdio(priv->muxval);
+	ls2080a_qds_mux_mdio(priv->muxval);

 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
 }

-static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 				  int regnum, u16 value)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;

-	ls2085a_qds_mux_mdio(priv->muxval);
+	ls2080a_qds_mux_mdio(priv->muxval);

 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 }

-static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;

 	return priv->realbus->reset(priv->realbus);
 }

-static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
 {
-	struct ls2085a_qds_mdio *pmdio;
+	struct ls2080a_qds_mdio *pmdio;
 	struct mii_dev *bus = mdio_alloc();

 	if (!bus) {
-		printf("Failed to allocate ls2085a_qds MDIO bus\n");
+		printf("Failed to allocate ls2080a_qds MDIO bus\n");
 		return -1;
 	}

 	pmdio = malloc(sizeof(*pmdio));
 	if (!pmdio) {
-		printf("Failed to allocate ls2085a_qds private data\n");
+		printf("Failed to allocate ls2080a_qds private data\n");
 		free(bus);
 		return -1;
 	}

-	bus->read = ls2085a_qds_mdio_read;
-	bus->write = ls2085a_qds_mdio_write;
-	bus->reset = ls2085a_qds_mdio_reset;
-	sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
+	bus->read = ls2080a_qds_mdio_read;
+	bus->write = ls2080a_qds_mdio_write;
+	bus->reset = ls2080a_qds_mdio_reset;
+	sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));

 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);

@ -511,7 +511,7 @@ static void initialize_dpmac_to_slot(void)
 	}
 }

-void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 {
 	int lane, slot;
 	struct mii_dev *bus;
@ -632,7 +632,7 @@ serdes2:
 	}
 }

-void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
 {
 	int lane = 0, slot;
 	struct mii_dev *bus;
@ -706,7 +706,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
 	qsgmii_configure_repeater(dpmac_id);
 }

-void ls2085a_handle_phy_interface_xsgmii(int i)
+void ls2080a_handle_phy_interface_xsgmii(int i)
 {
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@ -725,7 +725,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i)
 		 * error.
 		 */
 		wriop_set_phy_address(i, i + 4);
-		ls2085a_qds_enable_SFP_TX(SFP_TX);
+		ls2080a_qds_enable_SFP_TX(SFP_TX);

 		break;
 	default:
@ -778,25 +778,25 @@ int board_eth_init(bd_t *bis)
 	fm_memac_mdio_init(bis, memac_mdio1_info);

 	/* Register the muxing front-ends to the MDIO buses */
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);

-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);

 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 		switch (wriop_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_QSGMII:
-			ls2085a_handle_phy_interface_qsgmii(i);
+			ls2080a_handle_phy_interface_qsgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_SGMII:
-			ls2085a_handle_phy_interface_sgmii(i);
+			ls2080a_handle_phy_interface_sgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_XGMII:
-			ls2085a_handle_phy_interface_xsgmii(i);
+			ls2080a_handle_phy_interface_xsgmii(i);
 			break;
 		default:
 			break;
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@ -21,7 +21,7 @@
 #include <hwconfig.h>

 #include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"

 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
@ -226,11 +226,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }

 int dram_init(void)
--- a/board/freescale/ls2080aqds/ls2080aqds_qixis.h
+++ b/board/freescale/ls2080aqds/ls2080aqds_qixis.h
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@ -1,8 +1,8 @@

-if TARGET_LS2085AQDS
+if TARGET_LS2080ARDB

 config SYS_BOARD
-	default "ls2085aqds"
+	default "ls2080ardb"

 config SYS_VENDOR
 	default "freescale"
@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"

 config SYS_CONFIG_NAME
-	default "ls2085aqds"
+	default "ls2080ardb"

 endif
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@ -0,0 +1,8 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080ardb/
+F:	board/freescale/ls2080a/ls2080ardb.c
+F:	include/configs/ls2080ardb.h
+F:	configs/ls2080ardb_defconfig
+F:	configs/ls2080ardb_nand_defconfig
--- a/board/freescale/ls2080ardb/Makefile
+++ b/board/freescale/ls2080ardb/Makefile
@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #

-obj-y += ls2085ardb.o eth_ls2085rdb.o
+obj-y += ls2080ardb.o eth_ls2080rdb.o
 obj-y += ddr.o
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@ -1,17 +1,17 @@
 Overview
 --------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.

-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.

-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:

 - Eight 64-bit ARM Cortex-A57 CPUs
 - 1 MB platform cache with ECC
@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features:
 - Service processor (SP) provides pre-boot initialization and secure-boot
  capabilities

- LS2085ARDB board Overview
+ LS2080ARDB board Overview
 -----------------------
 - SERDES Connections, 16 lanes supporting:
      - PCI Express - 3.0
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;
@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis)

 		break;
 	default:
-		printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
 		       srds_s1);
 		break;
 	}
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@ -20,7 +20,7 @@
 #include <asm/arch/soc.h>

 #include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
+#include "ls2080ardb_qixis.h"

 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
@ -192,11 +192,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }

 int dram_init(void)
--- a/board/freescale/ls2080ardb/ls2080ardb_qixis.h
+++ b/board/freescale/ls2080ardb/ls2080ardb_qixis.h
--- a/board/freescale/ls2085a/MAINTAINERS
+++ b/board/freescale/ls2085a/MAINTAINERS
@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	York Sun <yorksun@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085a/
-F:	include/configs/ls2085a_emu.h
-F:	configs/ls2085a_emu_defconfig
-F:	include/configs/ls2085a_simu.h
-F:	configs/ls2085a_simu_defconfig
--- a/board/freescale/ls2085a/Makefile
+++ b/board/freescale/ls2085a/Makefile
@ -1,8 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o
--- a/board/freescale/ls2085aqds/MAINTAINERS
+++ b/board/freescale/ls2085aqds/MAINTAINERS
@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085aqds/
-F:	board/freescale/ls2085a/ls2085aqds.c
-F:	include/configs/ls2085aqds.h
-F:	configs/ls2085aqds_defconfig
-F:	configs/ls2085aqds_nand_defconfig
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085ardb/
-F:	board/freescale/ls2085a/ls2085ardb.c
-F:	include/configs/ls2085ardb.h
-F:	configs/ls2085ardb_defconfig
-F:	configs/ls2085ardb_nand_defconfig
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_EMU=y
+CONFIG_TARGET_LS2080A_EMU=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_SIMU=y
+CONFIG_TARGET_LS2080A_SIMU=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080AQDS=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
 # CONFIG_CMD_SETEXPR is not set
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080ARDB=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
 # CONFIG_CMD_SETEXPR is not set
--- a/doc/README.fsl-trustzone-components
+++ b/doc/README.fsl-trustzone-components
@ -1,4 +1,4 @@
-Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
+Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like
 TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
 Address Space Controller).

@ -7,7 +7,7 @@ is left to a root-of-trust security software layer (running in EL3
 privilege mode), but still some configurations of these peripherals
 might be required while the bootloader is executing in EL3 privilege
 mode. The following sections define how to turn on these features for
-LS2085A like SoCs.
+LS2080A like SoCs.

 TZPC-BP147 (TrustZone Protection Controller)
 ============================================
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		goto step2;

 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	/* A008336 only applies to general DDR controllers */
 	if ((ctrl_num == 0) || (ctrl_num == 1))
 #endif
 		ddr_out32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A
 	/* A008514 only applies to DP-DDR controler */
 	if (ctrl_num == 2)
 #endif
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@ -1147,7 +1147,10 @@ static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	switch (argv[1][0]) {
 	case 's': {
 			char sub_cmd;
-			u64 mc_fw_addr, mc_dpc_addr, aiop_fw_addr;
+			u64 mc_fw_addr, mc_dpc_addr;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+			u64 aiop_fw_addr;
+#endif

 			sub_cmd = argv[2][0];
 			switch (sub_cmd) {
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@ -6,4 +6,4 @@

 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
-obj-$(CONFIG_LS2085A) += ls2085a.o
+obj-$(CONFIG_LS2080A) += ls2080a.o
--- a/drivers/net/ldpaa_eth/ls2080a.c
+++ b/drivers/net/ldpaa_eth/ls2080a.c
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@ -665,7 +665,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
 }
 #endif

-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_LS2080A

 void pcie_set_available_streamids(void *blob, const char *pcie_path,
 				  u32 *stream_ids, int count)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@ -11,7 +11,7 @@
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH3
-#define CONFIG_LS2085A
+#define CONFIG_LS2080A
 #define CONFIG_MP
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
@ -20,7 +20,7 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974

-#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/ls2080a_stream_id.h>
 #include <asm/arch/config.h>
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
 #define	CONFIG_SYS_HAS_SERDES
@ -80,6 +80,7 @@
 #define CPU_RELEASE_ADDR		secondary_boot_func

 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
 /*
 * DDR controller use 0 as the base address for binding.
@ -88,6 +89,7 @@
 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
 #define CONFIG_DP_DDR_CTRL		2
 #define CONFIG_DP_DDR_NUM_CTRLS		1
+#endif

 /* Generic Timer Definitions */
 /*
@ -182,8 +184,10 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#ifndef CONFIG_LS2080A
 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+#endif

 /*
 * Carve out a DDR region which will not be used by u-boot/Linux
@ -204,7 +208,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_PCIE3		/* PCIE controler 3 */
 #define CONFIG_PCIE4		/* PCIE controler 4 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
+#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"

 #define CONFIG_SYS_PCI_64BIT

--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@ -7,10 +7,10 @@
 #ifndef __LS2_EMU_H
 #define __LS2_EMU_H

-#include "ls2085a_common.h"
+#include "ls2080a_common.h"

-#define CONFIG_IDENT_STRING		" LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-EMU"
+#define CONFIG_IDENT_STRING		" LS2080A-EMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2080A-EMU"

 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
@ -27,7 +27,9 @@
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		1
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif

 #define CONFIG_FSL_DDR_SYNC_REFRESH

--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@ -7,10 +7,10 @@
 #ifndef __LS2_SIMU_H
 #define __LS2_SIMU_H

-#include "ls2085a_common.h"
+#include "ls2080a_common.h"

-#define CONFIG_IDENT_STRING		" LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
+#define CONFIG_IDENT_STRING		" LS2080A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2080A-SIMU"

 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
@ -20,7 +20,9 @@

 #define CONFIG_DIMM_SLOTS_PER_CTLR		1
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif

 /* SMSC 91C111 ethernet configuration */
 #define CONFIG_SMC91111
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@ -7,7 +7,7 @@
 #ifndef __LS2_QDS_H
 #define __LS2_QDS_H

-#include "ls2085a_common.h"
+#include "ls2080a_common.h"

 #define CONFIG_DISPLAY_BOARDINFO

@ -35,7 +35,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		2
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 #define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@ -7,7 +7,7 @@
 #ifndef __LS2_RDB_H
 #define __LS2_RDB_H

-#include "ls2085a_common.h"
+#include "ls2080a_common.h"

 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX       2
@ -37,7 +37,9 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR		2
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
 #define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@ -54,9 +54,9 @@ struct fsl_xhci {
 #if defined(CONFIG_LS102XA)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-#elif defined(CONFIG_LS2085A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
+#elif defined(CONFIG_LS2080A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #endif

 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \