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x86: chromebook_link: Enable GPIO support

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Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2014-11-12 22:42:25 -07:00
parent 1b4f25ff8e
commit 437c2b7cd0
3 changed files with 111 additions and 3 deletions
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3
arch/x86/dts/link.dts
View File

@ -14,18 +14,21 @@
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};

107
board/google/chromebook_link/link.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <asm/gpio.h>
int arch_early_init_r(void)
{
@ -15,3 +16,109 @@ int board_early_init_r(void)
{
return 0;
}
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
.gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
.gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
.gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
.gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
.gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio1 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio7 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio12 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
.gpio15 = GPIO_INVERT,
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio36 = GPIO_DIR_OUTPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio36 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_map link_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};
int board_early_init_f(void)
{
ich_gpio_set_gpio_map(&link_gpio_map);
return 0;
}

4
include/configs/chromebook_link.h
View File

@ -19,6 +19,7 @@
#define CONFIG_SYS_CAR_SIZE (128 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_X86_RESET_VECTOR
@ -40,9 +41,6 @@
* follow-on patches in this series. Add undefs here to avoid every patch
* having to put things back into x86-common.h
*/
#undef CONFIG_INTEL_ICH6_GPIO
#undef CONFIG_DM_GPIO
#undef CONFIG_CMD_GPIO
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#undef CONFIG_ICH_SPI