net: dwc_eth_qos: Fully rewrite RX descriptor field 3
The RX descriptor field 3 should contain only OWN and BUF1V bits before being used for receiving data by the DMA engine. However, right now, if the descriptor was already used for receiving data and is being cleared, the field 3 is only modified and the aforementioned two bits are ORRed into the field. This could lead to a residual dirty bits being left in the field 3 from previous transfer, and it generally does. Fully set the field 3 instead to clear those residual dirty bits. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com>
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@ -1288,7 +1288,7 @@ static int eqos_start(struct udevice *dev)
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struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
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rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
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(i * EQOS_MAX_PACKET_SIZE));
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rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
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rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
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}
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eqos->config->ops->eqos_flush_desc(eqos->descs);
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@ -1482,7 +1482,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
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* writes to the rest of the descriptor too.
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*/
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mb();
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rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
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rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
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eqos->config->ops->eqos_flush_desc(rx_desc);
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writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
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