PXA: Remove "xsengine" board
This board is broken and it's not possible to repair it. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
parent
736947847d
commit
4262a7c934
@ -1,51 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := xsengine.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0xA3F80000
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@ -1,470 +0,0 @@
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/*
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* (C) Copyright 2002
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* Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <linux/byteorder/swab.h>
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#define SWAP(x) __swab32(x)
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Functions */
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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int i;
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ulong size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
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switch (i) {
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case 0:
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flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
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break;
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case 1:
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flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
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flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
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break;
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default:
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panic ("configured too many flash banks!\n");
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break;
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}
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size += flash_info[i].size;
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}
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/* Protect monitor and environment sectors */
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flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
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flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) return;
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
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info->protect[i] = 0;
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
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break;
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case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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{
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short i;
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ulong value;
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ulong base = (ulong)addr;
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/* Write auto select command: read Manufacturer ID */
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addr[0x0555] = 0x00AA00AA;
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addr[0x02AA] = 0x00550055;
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addr[0x0555] = 0x00900090;
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value = addr[0];
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debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
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switch (value) {
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case AMD_MANUFACT:
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debug ("Manufacturer: AMD\n");
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info->flash_id = FLASH_MAN_AMD;
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break;
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case FUJ_MANUFACT:
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debug ("Manufacturer: FUJITSU\n");
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info->flash_id = FLASH_MAN_FUJ;
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break;
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default:
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debug ("Manufacturer: *** unknown ***\n");
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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value = addr[1]; /* device ID */
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debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
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switch (value) {
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case AMD_ID_MIRROR:
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debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
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addr[14], addr[15]);
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switch(addr[14]) {
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case AMD_ID_LV640U_2:
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if (addr[15] != AMD_ID_LV640U_3) {
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debug ("Chip: AMLV640U -> unknown\n");
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info->flash_id = FLASH_UNKNOWN;
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} else {
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debug ("Chip: AMLV640U\n");
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info->flash_id += FLASH_AMLV640U;
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info->sector_count = 128;
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info->size = 0x01000000;
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}
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break; /* => 16 MB */
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case AMD_ID_GL064MT_2:
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if (addr[15] != AMD_ID_GL064MT_3) {
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debug ("Chip: S29GL064M-R3 -> unknown\n");
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info->flash_id = FLASH_UNKNOWN;
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} else {
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debug ("Chip: S29GL064M-R3\n");
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info->flash_id += FLASH_S29GL064M;
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info->sector_count = 128;
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info->size = 0x01000000;
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}
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break; /* => 16 MB */
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default:
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debug ("Chip: *** unknown ***\n");
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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/* set up sector start address table */
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switch (value) {
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case AMD_ID_MIRROR:
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switch (info->flash_id & FLASH_TYPEMASK) {
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/* only known types here - no default */
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case FLASH_AMLV128U:
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case FLASH_AMLV640U:
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case FLASH_AMLV320U:
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base;
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base += 0x20000;
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}
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break;
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case FLASH_AMLV320B:
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base;
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/*
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* The first 8 sectors are 8 kB,
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* all the other ones are 64 kB
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*/
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base += (i < 8)
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? 2 * ( 8 << 10)
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: 2 * (64 << 10);
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}
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break;
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}
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break;
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default:
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return (0);
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break;
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}
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#if 0
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* D0 = 1 if protected */
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addr = (volatile unsigned long *)(info->start[i]);
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info->protect[i] = addr[2] & 1;
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}
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#endif
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/*
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* Prevent writes to uninitialized FLASH.
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*/
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if (info->flash_id != FLASH_UNKNOWN) {
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addr = (volatile unsigned long *)info->start[0];
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*addr = 0x00F000F0; /* reset bank */
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}
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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vu_long *addr = (vu_long*)(info->start[0]);
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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if ((info->flash_id == FLASH_UNKNOWN) ||
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(info->flash_id > FLASH_AMD_COMP)) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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l_sect = -1;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr[0x0555] = 0x00AA00AA;
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addr[0x02AA] = 0x00550055;
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addr[0x0555] = 0x00800080;
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addr[0x0555] = 0x00AA00AA;
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addr[0x02AA] = 0x00550055;
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (vu_long*)(info->start[sect]);
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addr[0] = 0x00300030;
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l_sect = sect;
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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/*
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* We wait for the last triggered sector
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*/
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if (l_sect < 0)
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goto DONE;
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start = get_timer (0);
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last = start;
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addr = (vu_long*)(info->start[l_sect]);
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while ((addr[0] & 0x00800080) != 0x00800080) {
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return 1;
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}
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/* show that we're waiting */
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if ((now - last) > 100000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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DONE:
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/* reset to read mode */
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addr = (volatile unsigned long *)info->start[0];
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addr[0] = 0x00F000F0; /* reset bank */
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printf (" done\n");
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return 0;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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if ((rc = write_word(info, wp, SWAP(data))) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i=0; i<4; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_word(info, wp, SWAP(data))) != 0) {
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return (rc);
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}
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return (0);
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}
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|
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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return (write_word(info, wp, SWAP(data)));
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}
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|
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
|
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static int write_word (flash_info_t *info, ulong dest, ulong data)
|
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{
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vu_long *addr = (vu_long*)(info->start[0]);
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ulong start;
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int flag;
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/* Check if Flash is (sufficiently) erased */
|
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if ((*((vu_long *)dest) & data) != data) {
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return (2);
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}
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||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
addr[0x0555] = 0x00A000A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
@ -1,221 +0,0 @@
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* ---- GPIO INITIALISATION ---- */
|
||||
/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
|
||||
|
||||
/* General purpose set registers */
|
||||
ldr r0, =GPSR0
|
||||
ldr r1, =CONFIG_SYS_GPSR0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPSR1
|
||||
ldr r1, =CONFIG_SYS_GPSR1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPSR2
|
||||
ldr r1, =CONFIG_SYS_GPSR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General purpose clear registers */
|
||||
ldr r0, =GPCR0
|
||||
ldr r1, =CONFIG_SYS_GPCR0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPCR1
|
||||
ldr r1, =CONFIG_SYS_GPCR1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPCR2
|
||||
ldr r1, =CONFIG_SYS_GPCR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General rising edge registers */
|
||||
ldr r0, =GRER0
|
||||
ldr r1, =CONFIG_SYS_GRER0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GRER1
|
||||
ldr r1, =CONFIG_SYS_GRER1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GRER2
|
||||
ldr r1, =CONFIG_SYS_GRER2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General falling edge registers */
|
||||
ldr r0, =GFER0
|
||||
ldr r1, =CONFIG_SYS_GFER0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GFER1
|
||||
ldr r1, =CONFIG_SYS_GFER1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GFER2
|
||||
ldr r1, =CONFIG_SYS_GFER2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General edge detect registers */
|
||||
ldr r0, =GPDR0
|
||||
ldr r1, =CONFIG_SYS_GPDR0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPDR1
|
||||
ldr r1, =CONFIG_SYS_GPDR1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPDR2
|
||||
ldr r1, =CONFIG_SYS_GPDR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General alternate function registers */
|
||||
ldr r0, =GAFR0_L /* [0:15] */
|
||||
ldr r1, =CONFIG_SYS_GAFR0_L_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GAFR0_U /* [31:16] */
|
||||
ldr r1, =CONFIG_SYS_GAFR0_U_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GAFR1_L /* [47:32] */
|
||||
ldr r1, =CONFIG_SYS_GAFR1_L_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GAFR1_U /* [63:48] */
|
||||
ldr r1, =CONFIG_SYS_GAFR1_U_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GAFR2_L /* [79:64] */
|
||||
ldr r1, =CONFIG_SYS_GAFR2_L_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GAFR2_U /* [80] */
|
||||
ldr r1, =CONFIG_SYS_GAFR2_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* General purpose direction registers */
|
||||
ldr r0, =GPDR0
|
||||
ldr r1, =CONFIG_SYS_GPDR0_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPDR1
|
||||
ldr r1, =CONFIG_SYS_GPDR1_VAL
|
||||
str r1, [r0]
|
||||
ldr r0, =GPDR2
|
||||
ldr r1, =CONFIG_SYS_GPDR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* Power manager sleep status */
|
||||
ldr r0, =PSSR
|
||||
ldr r1, =CONFIG_SYS_PSSR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* ---- MEMORY INITIALISATION ---- */
|
||||
/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
|
||||
/* pause for 200 uSecs- allow internal clocks to settle */
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
mem_init:
|
||||
/* get memory controller base address */
|
||||
ldr r1, =MEMC_BASE
|
||||
|
||||
/* ---- FLASH INITIALISATION ---- */
|
||||
/* Write MSC0 and read back to ensure data change is accepted by cpu */
|
||||
ldr r2, =CONFIG_SYS_MSC0_VAL
|
||||
str r2, [r1, #MSC0_OFFSET]
|
||||
ldr r2, [r1, #MSC0_OFFSET]
|
||||
|
||||
/* ---- SDRAM INITIALISATION ---- */
|
||||
/* get the MDREFR settings */
|
||||
ldr r2, =CONFIG_SYS_MDREFR_VAL
|
||||
str r2, [r1, #MDREFR_OFFSET]
|
||||
|
||||
/* fetch platform value of MDCNFG */
|
||||
ldr r2, =CONFIG_SYS_MDCNFG_VAL
|
||||
|
||||
/* disable all sdram banks */
|
||||
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
|
||||
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
|
||||
|
||||
/* write initial value of MDCNFG, w/o enabling sdram banks */
|
||||
str r2, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
/* pause for 200 uSecs */
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* about 200 usec */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
/* Access memory *not yet enabled* for CBR refresh cycles (8) */
|
||||
/* CBR is generated for all banks */
|
||||
|
||||
ldr r2, =CONFIG_SYS_DRAM_BASE
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
|
||||
/* get memory controller base address */
|
||||
ldr r2, =MEMC_BASE
|
||||
|
||||
/* Enable SDRAM bank 0 in MDCNFG register */
|
||||
ldr r2, [r1, #MDCNFG_OFFSET]
|
||||
orr r2, r2, #MDCNFG_DE0
|
||||
str r2, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
|
||||
ldr r2, =CONFIG_SYS_MDMRS_VAL
|
||||
str r2, [r1, #MDMRS_OFFSET]
|
||||
|
||||
/* ---- INTERRUPT INITIALISATION ---- */
|
||||
/* Disable (mask) all interrupts at the interrupt controller */
|
||||
/* clear the interrupt level register (use IRQ, not FIQ) */
|
||||
mov r1, #0
|
||||
ldr r2, =ICLR
|
||||
str r1, [r2]
|
||||
|
||||
/* Set interrupt mask register */
|
||||
ldr r1, =CONFIG_SYS_ICMR_VAL
|
||||
ldr r2, =ICMR
|
||||
str r1, [r2]
|
||||
|
||||
/* ---- CLOCK INITIALISATION ---- */
|
||||
/* Disable the peripheral clocks, and set the core clock */
|
||||
|
||||
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
|
||||
ldr r1, =CKEN
|
||||
mov r2, #0
|
||||
str r2, [r1]
|
||||
|
||||
/* set core clocks */
|
||||
ldr r2, =CONFIG_SYS_CCCR_VAL
|
||||
ldr r1, =CCCR
|
||||
str r2, [r1]
|
||||
|
||||
#ifdef ENABLE32KHZ
|
||||
/* enable the 32Khz oscillator for RTC and PowerManager */
|
||||
ldr r1, =OSCC
|
||||
mov r2, #OSCC_OON
|
||||
str r2, [r1]
|
||||
|
||||
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
|
||||
60:
|
||||
ldr r2, [r1]
|
||||
ands r2, r2, #1
|
||||
beq 60b
|
||||
#endif
|
||||
|
||||
/* Turn on needed clocks */
|
||||
ldr r1, =CKEN
|
||||
ldr r2, =CONFIG_SYS_CKEN_VAL
|
||||
str r2, [r1]
|
||||
|
||||
mov pc, r10
|
||||
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
/* memory and cpu-speed are setup before relocation */
|
||||
/* so we do _nothing_ here */
|
||||
|
||||
/* arch number */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init (void)
|
||||
{
|
||||
setenv ("stdout", "serial");
|
||||
setenv ("stderr", "serial");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_SMC91111
|
||||
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
@ -401,7 +401,6 @@ lpd7a400 arm lh7a40x lpd7a40x
|
||||
lpd7a404 arm lh7a40x lpd7a40x
|
||||
colibri_pxa270 arm pxa
|
||||
pxa255_idp arm pxa
|
||||
xsengine arm pxa
|
||||
zylonite arm pxa
|
||||
atngw100 avr32 at32ap - atmel at32ap700x
|
||||
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
|
||||
|
||||
@ -1,216 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_XSENGINE 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x04000000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
|
||||
|
||||
/* FLASH organization */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=xsengine-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
|
||||
*/
|
||||
|
||||
/* Environment settings */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
|
||||
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/* Hardware drivers */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_SMC91111
|
||||
#define CONFIG_SMC91111_BASE 0x04000300
|
||||
#define CONFIG_SMC_USE_32_BIT 1
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_PXA_SERIAL
|
||||
#define CONFIG_FFUART 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.1.50
|
||||
#define CONFIG_SERVERIP 192.168.1.2
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_PXA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000
|
||||
#endif
|
||||
|
||||
/* Stack sizes - The stack sizes are set up in start.S using the settings below */
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* GP set register */
|
||||
#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
|
||||
#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */
|
||||
#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
|
||||
|
||||
/* GP clear register */
|
||||
#define CONFIG_SYS_GPCR0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GPCR1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GPCR2_VAL 0x00000000
|
||||
|
||||
/* GP direction register */
|
||||
#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
|
||||
#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
|
||||
#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
|
||||
|
||||
/* GP rising edge detect register */
|
||||
#define CONFIG_SYS_GRER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER2_VAL 0x00000000
|
||||
|
||||
/* GP falling edge detect register */
|
||||
#define CONFIG_SYS_GFER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER2_VAL 0x00000000
|
||||
|
||||
/* GP alternate function register */
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */
|
||||
#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */
|
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
|
||||
#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */
|
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
|
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */
|
||||
#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/* Memory settings */
|
||||
#define CONFIG_SYS_MSC0_VAL 0x25F425F0
|
||||
|
||||
/* MDCNFG: SDRAM Configuration Register */
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x000009C9
|
||||
|
||||
/* MDREFR: SDRAM Refresh Control Register */
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x00018018
|
||||
|
||||
/* MDMRS: Mode Register Set Configuration Register */
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user