video: omap: rename LCD controller registers
Add more clarity by prefixing the name of the register to the bitfields. Signed-off-by: Dario Binacchi <dariobin@libero.it>
This commit is contained in:
Dario Binacchi
Lokesh Vutla
parent
017295f31d
commit
41f76a01f3
@ -26,42 +26,42 @@
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCD_RASTER_MODE BIT(0)
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#define LCD_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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#define LCDC_CTRL_RASTER_MODE BIT(0)
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#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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/* LCD Clock Enable Register */
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#define LCD_CORECLKEN BIT(0)
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#define LCD_LIDDCLKEN BIT(1)
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#define LCD_DMACLKEN BIT(2)
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#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0)
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#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1)
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#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2)
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/* LCD DMA Control Register */
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#define LCD_DMA_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
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#define LCD_DMA_BURST_1 0x0
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#define LCD_DMA_BURST_2 0x1
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#define LCD_DMA_BURST_4 0x2
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
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#define LCDC_DMA_CTRL_BURST_1 0x0
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#define LCDC_DMA_CTRL_BURST_2 0x1
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#define LCDC_DMA_CTRL_BURST_4 0x2
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#define LCDC_DMA_CTRL_BURST_8 0x3
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#define LCDC_DMA_CTRL_BURST_16 0x4
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/* LCD Timing_0 Register */
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#define LCD_HORMSB(x) (((((x) >> 4) - 1) & 0x40) >> 4)
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#define LCD_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCD_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCD_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCD_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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#define LCDC_RASTER_TIMING_0_HORMSB(x) (((((x) >> 4) - 1) & 0x40) >> 4)
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#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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/* LCD Timing_1 Register */
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#define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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#define LCD_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCD_VFP(x) (((x) & GENMASK(7, 0)) << 16)
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#define LCD_VBP(x) (((x) & GENMASK(7, 0)) << 24)
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#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24)
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/* LCD Timing_2 Register */
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#define LCD_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCD_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCD_INVMASK(x) ((x) & GENMASK(25, 20))
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#define LCD_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCD_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCDC_RASTER_TIMING_2_INVMASK(x) ((x) & GENMASK(25, 20))
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#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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/* LCD Raster Ctrl Register */
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#define LCD_RASTER_ENABLE BIT(0)
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#define LCD_TFT_MODE BIT(7)
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#define LCD_PALMODE_RAWDATA (0x02 << 20)
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#define LCD_TFT_24BPP_MODE BIT(25)
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#define LCD_TFT_24BPP_UNPACK BIT(26)
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#define LCDC_RASTER_CTRL_ENABLE BIT(0)
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#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
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#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
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#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
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#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
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/* Macro definitions */
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#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
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@ -131,10 +131,10 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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case 16:
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break;
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case 32:
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raster_ctrl |= LCD_TFT_24BPP_UNPACK;
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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raster_ctrl |= LCD_TFT_24BPP_MODE;
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
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break;
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default:
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pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
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@ -198,34 +198,35 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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debug("am335x-fb: wait for stable power ...\n");
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mdelay(panel->pup_delay);
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lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
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lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
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LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
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lcdhw->ctrl = LCDC_CTRL_CLK_DIVISOR(best_d) | LCDC_CTRL_RASTER_MODE;
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_fb1_base = gd->fb_base;
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lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
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lcdhw->lcddma_ctrl = LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
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lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
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LCD_HORMSB(panel->hactive) |
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LCD_HFPLSB(panel->hfp) |
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LCD_HBPLSB(panel->hbp) |
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LCD_HSWLSB(panel->hsw);
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lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
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LCD_VFP(panel->vfp) |
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LCD_VSW(panel->vsw) |
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LCD_VERLSB(panel->vactive);
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lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
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LCD_VERMSB(panel->vactive) |
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LCD_INVMASK(panel->pol) |
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LCD_HBPMSB(panel->hbp) |
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LCD_HFPMSB(panel->hfp) |
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lcdhw->raster_timing0 = LCDC_RASTER_TIMING_0_HORLSB(panel->hactive) |
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LCDC_RASTER_TIMING_0_HORMSB(panel->hactive) |
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LCDC_RASTER_TIMING_0_HFPLSB(panel->hfp) |
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LCDC_RASTER_TIMING_0_HBPLSB(panel->hbp) |
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LCDC_RASTER_TIMING_0_HSWLSB(panel->hsw);
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lcdhw->raster_timing1 = LCDC_RASTER_TIMING_1_VBP(panel->vbp) |
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LCDC_RASTER_TIMING_1_VFP(panel->vfp) |
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LCDC_RASTER_TIMING_1_VSW(panel->vsw) |
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LCDC_RASTER_TIMING_1_VERLSB(panel->vactive);
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lcdhw->raster_timing2 = LCDC_RASTER_TIMING_2_HSWMSB(panel->hsw) |
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LCDC_RASTER_TIMING_2_VERMSB(panel->vactive) |
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LCDC_RASTER_TIMING_2_INVMASK(panel->pol) |
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LCDC_RASTER_TIMING_2_HBPMSB(panel->hbp) |
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LCDC_RASTER_TIMING_2_HFPMSB(panel->hfp) |
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0x0000FF00; /* clk cycles for ac-bias */
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lcdhw->raster_ctrl = raster_ctrl |
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LCD_PALMODE_RAWDATA |
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LCD_TFT_MODE |
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LCD_RASTER_ENABLE;
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LCDC_RASTER_CTRL_PALMODE_RAWDATA |
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LCDC_RASTER_CTRL_TFT_MODE |
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LCDC_RASTER_CTRL_ENABLE;
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debug("am335x-fb: waiting picture to be stable.\n.");
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mdelay(panel->pon_delay);
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