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include/asm-ppc/cache.h
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89
include/asm-ppc/cache.h
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/*
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* include/asm-ppc/cache.h
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*/
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#ifndef __ARCH_PPC_CACHE_H
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#define __ARCH_PPC_CACHE_H
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#include <linux/config.h>
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#include <asm/processor.h>
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/* bytes per L1 cache line */
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#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
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#if defined(CONFIG_PPC64BRIDGE)
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#define L1_CACHE_BYTES 128
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#else
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#define L1_CACHE_BYTES 32
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#endif /* PPC64 */
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#else
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#define L1_CACHE_BYTES 16
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#endif /* !8xx || 8260 */
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define L1_CACHE_PAGES 8
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#ifdef MODULE
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#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
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#else
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#define __cacheline_aligned \
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__attribute__((__aligned__(L1_CACHE_BYTES), \
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__section__(".data.cacheline_aligned")))
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#endif
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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#ifdef CFG_INIT_RAM_LOCK
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extern void unlock_ram_in_cache(void);
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#endif /* CFG_INIT_RAM_LOCK */
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#endif /* __ASSEMBLY__ */
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/* prep registers for L2 */
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#define CACHECRBA 0x80000823 /* Cache configuration register address */
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#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
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#define L2CACHE_512KB 0x00 /* 512KB */
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#define L2CACHE_256KB 0x01 /* 256KB */
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#define L2CACHE_1MB 0x02 /* 1MB */
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#define L2CACHE_NONE 0x03 /* NONE */
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#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
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#ifdef CONFIG_8xx
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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#define IC_CST 560 /* Instruction cache control/status */
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#define IC_ADR 561 /* Address needed for some commands */
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#define IC_DAT 562 /* Read-only data register */
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#define DC_CST 568 /* Data cache control/status */
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#define DC_ADR 569 /* Address needed for some commands */
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#define DC_DAT 570 /* Read-only data register */
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/* Commands. Only the first few are available to the instruction cache.
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*/
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#define IDC_ENABLE 0x02000000 /* Cache enable */
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#define IDC_DISABLE 0x04000000 /* Cache disable */
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#define IDC_LDLCK 0x06000000 /* Load and lock */
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#define IDC_UNLINE 0x08000000 /* Unlock line */
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#define IDC_UNALL 0x0a000000 /* Unlock all */
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#define IDC_INVALL 0x0c000000 /* Invalidate all */
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#define DC_FLINE 0x0e000000 /* Flush data cache line */
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#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
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#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
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#define DC_SLES 0x05000000 /* Set little endian swap mode */
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#define DC_CLES 0x07000000 /* Clear little endian swap mode */
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/* Status.
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*/
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#define IDC_ENABLED 0x80000000 /* Cache is enabled */
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#define IDC_CERR1 0x00200000 /* Cache error 1 */
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#define IDC_CERR2 0x00100000 /* Cache error 2 */
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#define IDC_CERR3 0x00080000 /* Cache error 3 */
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#define DC_DFWT 0x40000000 /* Data cache is forced write through */
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#define DC_LES 0x20000000 /* Caches are little endian mode */
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#endif /* CONFIG_8xx */
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#endif
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218
include/galileo/core.h
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include/galileo/core.h
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/* Core.h - Basic core logic functions and definitions */
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/* Copyright Galileo Technology. */
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/*
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DESCRIPTION
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This header file contains simple read/write macros for addressing
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the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
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space). The macros take care of Big/Little endian conversions.
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*/
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#ifndef __INCcoreh
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#define __INCcoreh
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/* includes */
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#include "gt64260R.h"
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extern unsigned int INTERNAL_REG_BASE_ADDR;
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/*
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* GT-6426x variants
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*/
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#define GT_64260 0 /* includes both 64260A and 64260B */
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#define GT_64261 1
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#if (CFG_GT_6426x == GT_64260)
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#ifdef CONFIG_ETHER_PORT_MII
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#define GAL_ETH_DEVS 2
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#else
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#define GAL_ETH_DEVS 3
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#endif
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#elif (CFG_GT_6426x == GT_64261)
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#define GAL_ETH_DEVS 2
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#else
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#define GAL_ETH_DEVS 3 /* default to a 64260 */
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#endif
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/****************************************/
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/* GENERAL Definitions */
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/****************************************/
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#define NO_BIT 0x00000000
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#define _1K 0x00000400
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#define _2K 0x00000800
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#define _4K 0x00001000
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#define _8K 0x00002000
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#define _16K 0x00004000
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#define _32K 0x00008000
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#define _64K 0x00010000
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#define _128K 0x00020000
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#define _256K 0x00040000
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#define _512K 0x00080000
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#define _1M 0x00100000
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#define _2M 0x00200000
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#define _3M 0x00300000
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#define _4M 0x00400000
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#define _5M 0x00500000
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#define _6M 0x00600000
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#define _7M 0x00700000
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#define _8M 0x00800000
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#define _9M 0x00900000
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#define _10M 0x00a00000
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#define _11M 0x00b00000
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#define _12M 0x00c00000
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#define _13M 0x00d00000
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#define _14M 0x00e00000
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#define _15M 0x00f00000
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#define _16M 0x01000000
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#define _32M 0x02000000
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#define _64M 0x04000000
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#define _128M 0x08000000
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#define _256M 0x10000000
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#define _512M 0x20000000
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#define _1G 0x40000000
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#define _2G 0x80000000
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typedef enum _bool{false,true} bool;
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/* Little to Big endian conversion macros */
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#ifdef LE /* Little Endian */
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#define SHORT_SWAP(X) (X)
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#define WORD_SWAP(X) (X)
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#define LONG_SWAP(X) ((l64)(X))
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#else /* Big Endian */
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#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
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#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
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(((X)&0xff00)<<8)+ \
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(((X)&0xff0000)>>8)+ \
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(((X)&0xff000000)>>24)
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#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
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(((X)&0xff00ULL)<<40)+ \
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(((X)&0xff0000ULL)<<24)+ \
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(((X)&0xff000000ULL)<<8)+ \
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(((X)&0xff00000000ULL)>>8)+ \
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(((X)&0xff0000000000ULL)>>24)+ \
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(((X)&0xff000000000000ULL)>>40)+ \
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(((X)&0xff00000000000000ULL)>>56))
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#endif
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#ifndef NULL
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#define NULL 0
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#endif
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/* Those two definitions were defined to be compatible with MIPS */
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#define NONE_CACHEABLE 0x00000000
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#define CACHEABLE 0x00000000
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/* 750 cache line */
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#define CACHE_LINE_SIZE 32
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#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
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#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
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/* Read/Write to/from GT`s internal registers */
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#define GT_REG_READ(offset, pData) \
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*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
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INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
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*pData = WORD_SWAP(*pData)
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#define GTREGREAD(offset) \
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(WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
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INTERNAL_REG_BASE_ADDR | (offset))) ))
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#define GT_REG_WRITE(offset, data) \
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*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
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WORD_SWAP(data)
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/* Write 32/16/8 bit */
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#define WRITE_CHAR(address, data) \
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*((unsigned char *)(address)) = data
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#define WRITE_SHORT(address, data) \
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*((unsigned short *)(address)) = data
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#define WRITE_WORD(address, data) \
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*((unsigned int *)(address)) = data
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/* Read 32/16/8 bits - returns data in variable. */
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#define READ_CHAR(address, pData) \
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*pData = *((volatile unsigned char *)(address))
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#define READ_SHORT(address, pData) \
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*pData = *((volatile unsigned short *)(address))
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#define READ_WORD(address, pData) \
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*pData = *((volatile unsigned int *)(address))
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/* Read 32/16/8 bit - returns data direct. */
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#define READCHAR(address) \
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*((volatile unsigned char *)((address) | NONE_CACHEABLE))
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#define READSHORT(address) \
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*((volatile unsigned short *)((address) | NONE_CACHEABLE))
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#define READWORD(address) \
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*((volatile unsigned int *)((address) | NONE_CACHEABLE))
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/* Those two Macros were defined to be compatible with MIPS */
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#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
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#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
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/* SET_REG_BITS(regOffset,bits) -
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gets register offset and bits: a 32bit value. It set to logic '1' in the
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internal register the bits which given as an input example:
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SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
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'1' in register 0x840 while the other bits stays as is. */
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#define SET_REG_BITS(regOffset,bits) \
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*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
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regOffset) |= (unsigned int)WORD_SWAP(bits)
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/* RESET_REG_BITS(regOffset,bits) -
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gets register offset and bits: a 32bit value. It set to logic '0' in the
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internal register the bits which given as an input example:
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RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
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'0' in register 0x840 while the other bits stays as is. */
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#define RESET_REG_BITS(regOffset,bits) \
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*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
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| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
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#endif /* __INCcoreh */
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