arm: socfpga: cache: Enable D-Cache

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

board/altera/socfpga/socfpga_cyclone5.c

@@ -35,6 +35,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	icache_enable();
+	dcache_enable();
 
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

include/configs/socfpga_cyclone5.h

@@ -18,7 +18,6 @@
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 
 #define CONFIG_MISC_INIT_R
@@ -26,6 +25,7 @@
 #define CONFIG_SOCFPGA
 #define CONFIG_CLOCKS
 
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
 /* base address for .text section */