arch/arm, arch/powerpc: add # of SEC engines on the SOC
Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -144,6 +144,7 @@
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#define CONFIG_ARM_ERRATA_829520
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#define CONFIG_ARM_ERRATA_833471
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_LS1043A)
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_CACHELINE_SIZE 64
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@ -197,6 +198,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_A009929
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#define CONFIG_SYS_FSL_ERRATUM_A009942
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#define CONFIG_SYS_FSL_ERRATUM_A009660
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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@ -132,6 +132,7 @@
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
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#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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#elif defined(CONFIG_QEMU_E500)
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#define CONFIG_MAX_CPUS 1
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@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define CONFIG_SYS_FSL_DDRC_GEN3
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#endif
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#if !defined(CONFIG_PPC_C29X)
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#endif
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#endif /* _ASM_MPC85xx_CONFIG_H_ */
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@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
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while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
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CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
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+ offset * 0x20000)) >= 0) {
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+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
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fdt_del_node(blob, nodeoff);
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offset++;
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}
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