mtd: sf: Add support of sst26wf* flash ICs protection ops
sst26wf flash series block protection implementation differs from other SST series, so add specific implementation flash_lock/flash_unlock/flash_is_locked functions for sst26wf flash ICs. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Eugeniy Paltsev
Jagan Teki
parent
40df6b3e18
commit
3d4fed87a5
@ -87,6 +87,19 @@ enum spi_nor_option_flags {
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/* SST specific */
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#ifdef CONFIG_SPI_FLASH_SST
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#define SST26_CMD_READ_BPR 0x72
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#define SST26_CMD_WRITE_BPR 0x42
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#define SST26_BPR_8K_NUM 4
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#define SST26_MAX_BPR_REG_LEN (18 + 1)
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#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
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enum lock_ctl {
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SST26_CTL_LOCK,
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SST26_CTL_UNLOCK,
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SST26_CTL_CHECK
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};
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# define CMD_SST_BP 0x02 /* Byte Program */
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# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
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@ -16,6 +16,7 @@
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#include <spi.h>
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#include <spi_flash.h>
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#include <linux/log2.h>
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#include <linux/sizes.h>
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#include <dma.h>
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#include "sf_internal.h"
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@ -541,6 +542,164 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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}
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#ifdef CONFIG_SPI_FLASH_SST
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static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
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{
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switch (ctl) {
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case SST26_CTL_LOCK:
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cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
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break;
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case SST26_CTL_UNLOCK:
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cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
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break;
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case SST26_CTL_CHECK:
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return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
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}
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return false;
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}
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/*
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* sst26wf016/sst26wf032/sst26wf064 have next block protection:
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* 4x - 8 KByte blocks - read & write protection bits - upper addresses
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* 1x - 32 KByte blocks - write protection bits
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* rest - 64 KByte blocks - write protection bits
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* 1x - 32 KByte blocks - write protection bits
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* 4x - 8 KByte blocks - read & write protection bits - lower addresses
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*
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* We'll support only per 64k lock/unlock so lower and upper 64 KByte region
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* will be treated as single block.
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*/
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/*
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* Lock, unlock or check lock status of the flash region of the flash (depending
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* on the lock_ctl value)
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*/
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static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
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{
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u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
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bool lower_64k = false, upper_64k = false;
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u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
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int ret;
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/* Check length and offset for 64k alignment */
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if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
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return -EINVAL;
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if (ofs + len > flash->size)
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return -EINVAL;
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/* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
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if (flash->size != SZ_2M &&
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flash->size != SZ_4M &&
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flash->size != SZ_8M)
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return -EINVAL;
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bpr_size = 2 + (flash->size / SZ_64K / 8);
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cmd = SST26_CMD_READ_BPR;
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ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
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if (ret < 0) {
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printf("SF: fail to read block-protection register\n");
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return ret;
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}
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rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
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lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
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upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
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lower_64k = (ofs < SST26_BOUND_REG_SIZE);
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/* Lower bits in block-protection register are about 64k region */
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bpr_ptr = lptr_64k / SZ_64K - 1;
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/* Process 64K blocks region */
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while (lptr_64k < rptr_64k) {
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if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
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return EACCES;
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bpr_ptr++;
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lptr_64k += SZ_64K;
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}
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/* 32K and 8K region bits in BPR are after 64k region bits */
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bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
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/* Process lower 32K block region */
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if (lower_64k)
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if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
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return EACCES;
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bpr_ptr++;
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/* Process upper 32K block region */
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if (upper_64k)
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if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
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return EACCES;
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bpr_ptr++;
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/* Process lower 8K block regions */
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for (i = 0; i < SST26_BPR_8K_NUM; i++) {
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if (lower_64k)
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if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
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return EACCES;
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/* In 8K area BPR has both read and write protection bits */
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bpr_ptr += 2;
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}
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/* Process upper 8K block regions */
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for (i = 0; i < SST26_BPR_8K_NUM; i++) {
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if (upper_64k)
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if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
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return EACCES;
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/* In 8K area BPR has both read and write protection bits */
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bpr_ptr += 2;
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}
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/* If we check region status we don't need to write BPR back */
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if (ctl == SST26_CTL_CHECK)
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return 0;
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cmd = SST26_CMD_WRITE_BPR;
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ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
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if (ret < 0) {
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printf("SF: fail to write block-protection register\n");
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return ret;
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}
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return 0;
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}
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static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
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{
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return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
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}
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static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
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{
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return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
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}
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/*
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* Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
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* and negative on errors.
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*/
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static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
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{
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/*
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* is_locked function is used for check before reading or erasing flash
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* region, so offset and length might be not 64k allighned, so adjust
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* them to be 64k allighned as sst26_lock_ctl works only with 64k
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* allighned regions.
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*/
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ofs -= ofs & (SZ_64K - 1);
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len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
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return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
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}
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static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
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{
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struct spi_slave *spi = flash->spi;
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@ -1033,6 +1192,15 @@ int spi_flash_scan(struct spi_flash *flash)
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}
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#endif
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/* sst26wf series block protection implementation differs from other series */
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#if defined(CONFIG_SPI_FLASH_SST)
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if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
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flash->flash_lock = sst26_lock;
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flash->flash_unlock = sst26_unlock;
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flash->flash_is_locked = sst26_is_locked;
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}
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#endif
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/* Compute the flash size */
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flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
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flash->page_size = info->page_size;
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