video: Add support for TI's AM335x LCD-Controller
- Adds support for a minimal framebuffer driver of TI's AM335x SoC to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c) Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
This commit is contained in:
Hannes Petermaier
Anatolij Gustschin
parent
8d9eaafdd1
commit
3c5fabd139
@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
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obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
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obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
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obj-$(CONFIG_FORMIKE) += formike.o
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obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
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169
drivers/video/am335x-fb.c
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169
drivers/video/am335x-fb.c
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@ -0,0 +1,169 @@
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/*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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*
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* - supporting only 24bit RGB/TFT raster Mode (not using palette)
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* - sets up LCD controller as in 'am335x_lcdpanel' struct given
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* - starts output DMA from gd->fb_base buffer
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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#include "am335x-fb.h"
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#if !defined(LCD_CNTL_BASE)
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#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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#endif
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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#define LCD_RASTER_MODE 0x01
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/* LCD Clock Enable Register */
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#define LCD_CORECLKEN (0x01 << 0)
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#define LCD_LIDDCLKEN (0x01 << 1)
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#define LCD_DMACLKEN (0x01 << 2)
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/* LCD DMA Control Register */
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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
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#define LCD_DMA_BURST_1 0x0
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#define LCD_DMA_BURST_2 0x1
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#define LCD_DMA_BURST_4 0x2
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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/* LCD Timing_0 Register */
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#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
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#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16)
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#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10)
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#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4)
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#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4)
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/* LCD Timing_1 Register */
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#define LCD_VBP(x) ((x) << 24)
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#define LCD_VFP(x) ((x) << 16)
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#define LCD_VSW(x) (((x)-1) << 10)
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#define LCD_VERLSB(x) (((x)-1) & 0x3FF)
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/* LCD Timing_2 Register */
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#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21)
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#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16)
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#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4)
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#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
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#define LCD_INVMASK(x) ((x) & 0x3F00000)
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/* LCD Raster Ctrl Register */
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#define LCD_TFT_24BPP_MODE (1 << 25)
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#define LCD_TFT_24BPP_UNPACK (1 << 26)
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#define LCD_PALMODE_RAWDATA (0x10 << 20)
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#define LCD_TFT_MODE (0x01 << 7)
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#define LCD_RASTER_ENABLE (0x01 << 0)
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/* Macro definitions */
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#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
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struct am335x_lcdhw {
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unsigned int pid; /* 0x00 */
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unsigned int ctrl; /* 0x04 */
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unsigned int gap0; /* 0x08 */
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unsigned int lidd_ctrl; /* 0x0C */
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unsigned int lidd_cs0_conf; /* 0x10 */
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unsigned int lidd_cs0_addr; /* 0x14 */
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unsigned int lidd_cs0_data; /* 0x18 */
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unsigned int lidd_cs1_conf; /* 0x1C */
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unsigned int lidd_cs1_addr; /* 0x20 */
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unsigned int lidd_cs1_data; /* 0x24 */
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unsigned int raster_ctrl; /* 0x28 */
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unsigned int raster_timing0; /* 0x2C */
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unsigned int raster_timing1; /* 0x30 */
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unsigned int raster_timing2; /* 0x34 */
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unsigned int raster_subpanel; /* 0x38 */
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unsigned int raster_subpanel2; /* 0x3C */
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unsigned int lcddma_ctrl; /* 0x40 */
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unsigned int lcddma_fb0_base; /* 0x44 */
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unsigned int lcddma_fb0_ceiling; /* 0x48 */
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unsigned int lcddma_fb1_base; /* 0x4C */
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unsigned int lcddma_fb1_ceiling; /* 0x50 */
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unsigned int sysconfig; /* 0x54 */
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unsigned int irqstatus_raw; /* 0x58 */
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unsigned int irqstatus; /* 0x5C */
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unsigned int irqenable_set; /* 0x60 */
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unsigned int irqenable_clear; /* 0x64 */
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unsigned int gap1; /* 0x68 */
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unsigned int clkc_enable; /* 0x6C */
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unsigned int clkc_reset; /* 0x70 */
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};
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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DECLARE_GLOBAL_DATA_PTR;
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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return *line_length * panel_info.vl_row + 0x20;
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}
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int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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if (0 == gd->fb_base) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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return -1;
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}
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if (0 == panel) {
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printf("ERROR: missing ptr to am335x_lcdpanel!\n");
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return -1;
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}
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debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
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panel->hactive, panel->vactive, panel->bpp,
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panel->hfp, panel->hbp, panel->hsw);
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debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
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panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
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debug("using frambuffer at 0x%08x with size %d.\n",
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(unsigned int)gd->fb_base, FBSIZE(panel));
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/* palette default entry */
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memset((void *)gd->fb_base, 0, 0x20);
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*(unsigned int *)gd->fb_base = 0x4000;
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lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
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lcdhw->lcddma_fb1_base = gd->fb_base;
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lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
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lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
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lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
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LCD_HORMSB(panel->hactive) |
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LCD_HFPLSB(panel->hfp) |
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LCD_HBPLSB(panel->hbp) |
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LCD_HSWLSB(panel->hsw);
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lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
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LCD_VFP(panel->vfp) |
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LCD_VSW(panel->vsw) |
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LCD_VERLSB(panel->vactive);
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lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
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LCD_VERMSB(panel->vactive) |
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LCD_INVMASK(panel->pol) |
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LCD_HBPMSB(panel->hbp) |
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LCD_HFPMSB(panel->hfp) |
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0x0000FF00; /* clk cycles for ac-bias */
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lcdhw->raster_ctrl = LCD_TFT_24BPP_MODE |
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LCD_TFT_24BPP_UNPACK |
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LCD_PALMODE_RAWDATA |
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LCD_TFT_MODE |
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LCD_RASTER_ENABLE;
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gd->fb_base += 0x20; /* point fb behind palette */
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/* turn ON display through powercontrol function if accessible */
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if (0 != panel->panel_power_ctrl) {
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mdelay(panel->pon_delay);
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panel->panel_power_ctrl(1);
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}
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return 0;
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}
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67
drivers/video/am335x-fb.h
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67
drivers/video/am335x-fb.h
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@ -0,0 +1,67 @@
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/*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AM335X_FB_H
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#define AM335X_FB_H
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#define HSVS_CONTROL (0x01 << 25) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* opposite edges of pixel clock than
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* the lcd_pixel_o
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* 1 = lcd_lp and lcd_fp are driven
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* according to bit 24 Note that this
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* bit MUST be set to '0' for Passive
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* Matrix displays the edge timing is
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* fixed
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*/
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#define HSVS_RISEFALL (0x01 << 24) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* the rising edge of pixel clock (bit
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* 25 must be set to 1)
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* 1 = lcd_lp and lcd_fp are driven on
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* the falling edge of pixel clock (bit
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* 25 must be set to 1)
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*/
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#define DE_INVERT (0x01 << 23) /*
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* 0 = DE is low-active
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* 1 = DE is high-active
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*/
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#define PXCLK_INVERT (0x01 << 22) /*
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* 0 = pix-clk is high-active
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* 1 = pic-clk is low-active
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*/
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#define HSYNC_INVERT (0x01 << 21) /*
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* 0 = HSYNC is active high
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* 1 = HSYNC is avtive low
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*/
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#define VSYNC_INVERT (0x01 << 20) /*
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* 0 = VSYNC is active high
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* 1 = VSYNC is active low
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*/
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struct am335x_lcdpanel {
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unsigned int hactive; /* Horizontal active area */
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unsigned int vactive; /* Vertical active area */
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unsigned int bpp; /* bits per pixel */
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unsigned int hfp; /* Horizontal front porch */
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unsigned int hbp; /* Horizontal back porch */
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unsigned int hsw; /* Horizontal Sync Pulse Width */
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unsigned int vfp; /* Vertical front porch */
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unsigned int vbp; /* Vertical back porch */
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unsigned int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk_div; /* Pixel clock divider*/
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unsigned int pol; /* polarity of sync, clock signals */
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unsigned int pon_delay; /*
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* time in ms for turning on lcd after
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* initializing lcd-controller
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*/
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void (*panel_power_ctrl)(int); /* fp for power on/off display */
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};
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int am335xfb_init(struct am335x_lcdpanel *panel);
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#endif /* AM335X_FB_H */
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