arm: sync armada-xp dts files from Linux 5.0
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't got the new NAND driver the updating binding has not been included. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
Stefan Roese
parent
02f173ca15
commit
3c265bbe4d
@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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@ -8,50 +9,10 @@
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton64.dtsi"
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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@ -86,7 +47,7 @@
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pcie-mem-aperture = <0xf8000000 0x7e00000>;
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pcie-io-aperture = <0xffe00000 0x100000>;
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devbus-bootcs {
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devbus_bootcs: devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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@ -96,7 +57,7 @@
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status = "disabled";
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};
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devbus-cs0 {
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devbus_cs0: devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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@ -106,7 +67,7 @@
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status = "disabled";
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};
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devbus-cs1 {
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devbus_cs1: devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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@ -116,7 +77,7 @@
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status = "disabled";
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};
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devbus-cs2 {
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devbus_cs2: devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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@ -126,7 +87,7 @@
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status = "disabled";
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};
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devbus-cs3 {
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devbus_cs3: devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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@ -141,34 +102,13 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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u-boot,dm-pre-reloc;
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rtc@10300 {
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rtc: rtc@10300 {
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compatible = "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <50>;
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};
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spi0: spi@10600 {
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reg = <0x10600 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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reg = <0x10680 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
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@ -235,33 +175,38 @@
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msi-controller;
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};
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coherency-fabric@20200 {
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coherencyfab: coherency-fabric@20200 {
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compatible = "marvell,coherency-fabric";
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reg = <0x20200 0xb0>, <0x21010 0x1c>;
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};
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timer@20300 {
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timer: timer@20300 {
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
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};
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watchdog@20300 {
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watchdog: watchdog@20300 {
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reg = <0x20300 0x34>, <0x20704 0x4>;
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};
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pmsu@22000 {
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cpurst: cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x8>;
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};
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pmsu: pmsu@22000 {
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compatible = "marvell,armada-370-pmsu";
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reg = <0x22000 0x1000>;
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};
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usb@50000 {
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usb0: usb@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x500>;
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interrupts = <45>;
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status = "disabled";
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};
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usb@51000 {
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usb1: usb@51000 {
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compatible = "marvell,orion-ehci";
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reg = <0x51000 0x500>;
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interrupts = <46>;
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@ -275,7 +220,7 @@
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status = "disabled";
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};
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mdio: mdio {
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mdio: mdio@72004 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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@ -290,7 +235,7 @@
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status = "disabled";
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};
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sata@a0000 {
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sata: sata@a0000 {
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compatible = "marvell,armada-370-sata";
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reg = <0xa0000 0x5000>;
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interrupts = <55>;
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@ -309,7 +254,7 @@
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status = "disabled";
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};
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mvsdio@d4000 {
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sdio: mvsdio@d4000 {
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compatible = "marvell,orion-sdio";
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reg = <0xd4000 0x200>;
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interrupts = <54>;
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@ -321,6 +266,42 @@
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status = "disabled";
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};
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};
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spi0: spi@10600 {
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reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
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<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
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<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
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<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
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<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
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<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
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<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
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<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
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<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
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<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
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<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
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<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
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<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
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<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
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<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
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<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
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<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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};
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clocks {
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@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada XP development board
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* (DB-MV784MP-GP)
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@ -8,44 +9,6 @@
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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@ -68,11 +31,7 @@
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stdout-path = "serial0:115200n8";
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};
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aliases {
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spi0 = &spi0;
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};
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memory {
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memory@0 {
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device_type = "memory";
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/*
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* 8 GB of plug-in RAM modules by default.The amount
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@ -98,7 +57,10 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
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devbus-bootcs {
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status = "okay";
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@ -128,31 +90,9 @@
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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serial@12100 {
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status = "okay";
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@ -177,43 +117,33 @@
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status = "okay";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <16>;
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};
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phy1: ethernet-phy@1 {
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reg = <17>;
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};
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phy2: ethernet-phy@2 {
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reg = <18>;
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};
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phy3: ethernet-phy@3 {
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reg = <19>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <3>;
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};
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/* Front-side USB slot */
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@ -226,27 +156,72 @@
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status = "okay";
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};
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spi0: spi@10600 {
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bm@c0000 {
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status = "okay";
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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nand@d0000 {
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status = "okay";
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label = "pxa3xx_nand-0";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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};
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};
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bm-bppi {
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status = "okay";
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};
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};
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};
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&pciec {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
|
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@a,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <16>;
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||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -225,18 +225,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
@ -247,3 +235,15 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
@ -5,44 +6,6 @@
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78230 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
@ -207,25 +170,33 @@
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <17>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
@ -5,44 +6,6 @@
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78260 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
@ -294,29 +257,38 @@
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
@ -5,44 +6,6 @@
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
@ -333,29 +296,38 @@
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#pwm-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
|
||||
@ -1,13 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for Synology DS414
|
||||
*
|
||||
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
|
||||
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
|
||||
@ -42,36 +38,16 @@
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Connected to Marvell 88SX7042 SATA-II controller
|
||||
* handling the four disks.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Connected to EtronTech EJ168A XHCI controller
|
||||
* providing the two rear USB 3.0 ports.
|
||||
*/
|
||||
pcie@5,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
internal-regs {
|
||||
|
||||
@ -80,64 +56,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
spi-flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@00000000 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000d0000>; /* 832KB */
|
||||
};
|
||||
|
||||
partition@000c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000d0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@003a0000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x003a0000 0x00430000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@007d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
@ -179,16 +97,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
@ -215,7 +123,7 @@
|
||||
&sata3_pwr_pin &sata4_pwr_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
sata1_regulator: sata1-regulator {
|
||||
sata1_regulator: sata1-regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "SATA1 Power";
|
||||
@ -228,7 +136,7 @@
|
||||
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata2_regulator: sata2-regulator {
|
||||
sata2_regulator: sata2-regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "SATA2 Power";
|
||||
@ -241,7 +149,7 @@
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata3_regulator: sata3-regulator {
|
||||
sata3_regulator: sata3-regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "SATA3 Power";
|
||||
@ -254,7 +162,7 @@
|
||||
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata4_regulator: sata4-regulator {
|
||||
sata4_regulator: sata4-regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "SATA4 Power";
|
||||
@ -269,6 +177,39 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Connected to Marvell 88SX7042 SATA-II controller
|
||||
* handling the four disks.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Connected to EtronTech EJ168A XHCI controller
|
||||
* providing the two rear USB 3.0 ports.
|
||||
*/
|
||||
pcie@5,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&mdio {
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
sata1_pwr_pin: sata1-pwr-pin {
|
||||
marvell,pins = "mpp42";
|
||||
@ -335,3 +276,59 @@
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@0 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000d0000>; /* 832KB */
|
||||
};
|
||||
|
||||
partition@c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000d0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@3a0000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x003a0000 0x00430000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@7d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@7e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@7f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -126,40 +126,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
spi-flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
|
||||
fpga@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-generic-device";
|
||||
reg = <1>; /* Chip select 1 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
status = "okay";
|
||||
|
||||
fpga@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-generic-device";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
};
|
||||
|
||||
/* The LCD controller is only used on this board */
|
||||
lcd0: lcd-controller@e0000 {
|
||||
compatible = "marvell,armada-xp-lcd";
|
||||
@ -188,6 +154,41 @@
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
spi-flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
|
||||
fpga@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-generic-device";
|
||||
reg = <1>; /* Chip select 1 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
|
||||
fpga@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-generic-device";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <27777777>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
@ -8,44 +9,6 @@
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
@ -53,6 +16,9 @@
|
||||
#include "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
@ -71,12 +37,12 @@
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
sdramc@1400 {
|
||||
sdramc: sdramc@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
L2: l2-cache@8000 {
|
||||
compatible = "marvell,aurora-system-cache";
|
||||
reg = <0x08000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
@ -85,29 +51,6 @@
|
||||
wt-override;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
};
|
||||
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
uart2: serial@12200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
@ -132,7 +75,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
systemc: system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x500>;
|
||||
};
|
||||
@ -150,7 +93,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
thermal@182b0 {
|
||||
thermal: thermal@182b0 {
|
||||
compatible = "marvell,armadaxp-thermal";
|
||||
reg = <0x182b0 0x4
|
||||
0x184d0 0x4>;
|
||||
@ -164,25 +107,9 @@
|
||||
clocks = <&coreclk 1>;
|
||||
};
|
||||
|
||||
interrupt-controller@20a00 {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-xp-timer";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-xp-wdt";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x20>;
|
||||
cpu-config@21000 {
|
||||
compatible = "marvell,armada-xp-cpu-config";
|
||||
reg = <0x21000 0x8>;
|
||||
};
|
||||
|
||||
eth2: ethernet@30000 {
|
||||
@ -193,15 +120,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
clocks = <&gateclk 18>;
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
usb@52000 {
|
||||
usb2: usb@52000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x52000 0x500>;
|
||||
interrupts = <47>;
|
||||
@ -209,7 +128,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
xor1: xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
@ -237,7 +156,27 @@
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
};
|
||||
|
||||
xor@f0900 {
|
||||
cesa: crypto@90000 {
|
||||
compatible = "marvell,armada-xp-crypto";
|
||||
reg = <0x90000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <48>, <49>;
|
||||
clocks = <&gateclk 23>, <&gateclk 23>;
|
||||
clock-names = "cesa0", "cesa1";
|
||||
marvell,crypto-srams = <&crypto_sram0>,
|
||||
<&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x800>;
|
||||
};
|
||||
|
||||
bm: bm@c0000 {
|
||||
compatible = "marvell,armada-380-neta-bm";
|
||||
reg = <0xc0000 0xac>;
|
||||
clocks = <&gateclk 13>;
|
||||
internal-mem = <&bm_bppi>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor0: xor@f0900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xF0900 0x100
|
||||
0xF0B00 0x100>;
|
||||
@ -257,6 +196,35 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto_sram0: sa-sram0 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||
clocks = <&gateclk 23>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||
};
|
||||
|
||||
crypto_sram1: sa-sram1 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||
clocks = <&gateclk 23>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||
};
|
||||
|
||||
bm_bppi: bm-bppi {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&gateclk 13>;
|
||||
no-memory-wc;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
@ -269,6 +237,44 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
&mpic {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
||||
&timer {
|
||||
compatible = "marvell,armada-xp-timer";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
compatible = "marvell,armada-xp-wdt";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
&cpurst {
|
||||
reg = <0x20800 0x20>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&gateclk 18>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ge0_gmii_pins: ge0-gmii-pins {
|
||||
marvell,pins =
|
||||
@ -309,6 +315,12 @@
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14",
|
||||
"mpp16", "mpp17";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
marvell,pins = "mpp42", "mpp43";
|
||||
marvell,function = "uart2";
|
||||
@ -319,3 +331,15 @@
|
||||
marvell,function = "uart3";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user