armv8: ls1012a: Add support of ls1012ardb board
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
9d044fcb8c
commit
3b6e3898c2
@ -705,6 +705,15 @@ config TARGET_LS1012AQDS
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1012ARDB
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bool "Support ls1012ardb"
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select ARM64
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help
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Support for Freescale LS1012ARDB platform.
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The LS1012A Reference design board (RDB) is a high-performance
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1021AQDS
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bool "Support ls1021aqds"
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select CPU_V7
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@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig"
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source "board/freescale/ls1021atwr/Kconfig"
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source "board/freescale/ls1043ardb/Kconfig"
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source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/mx23evk/Kconfig"
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source "board/freescale/mx25pdk/Kconfig"
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source "board/freescale/mx28evk/Kconfig"
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@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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fsl-ls1012a-qds.dtb
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fsl-ls1012a-qds.dtb \
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fsl-ls1012a-rdb.dtb
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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16
arch/arm/dts/fsl-ls1012a-rdb.dts
Normal file
16
arch/arm/dts/fsl-ls1012a-rdb.dts
Normal file
@ -0,0 +1,16 @@
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/*
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* Device Tree file for Freescale Layerscape-1012A family SoC.
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*
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* Copyright 2016, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "fsl-ls1012a-rdb.dtsi"
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/ {
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chosen {
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stdout-path = &duart0;
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};
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};
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39
arch/arm/dts/fsl-ls1012a-rdb.dtsi
Normal file
39
arch/arm/dts/fsl-ls1012a-rdb.dtsi
Normal file
@ -0,0 +1,39 @@
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/*
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* Device Tree Include file for Freescale Layerscape-1012A family SoC.
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*
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* Copyright 2016, Freescale Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/include/ "fsl-ls1012a.dtsi"
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/ {
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model = "LS1012A RDB Board";
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aliases {
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spi0 = &qspi;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&duart0 {
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status = "okay";
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};
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15
board/freescale/ls1012ardb/Kconfig
Normal file
15
board/freescale/ls1012ardb/Kconfig
Normal file
@ -0,0 +1,15 @@
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if TARGET_LS1012ARDB
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config SYS_BOARD
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default "ls1012ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1012ardb"
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endif
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6
board/freescale/ls1012ardb/MAINTAINERS
Normal file
6
board/freescale/ls1012ardb/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
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LS1012ARDB BOARD
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M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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S: Maintained
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F: board/freescale/ls1012ardb/
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F: include/configs/ls1012ardb.h
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F: configs/ls1012ardb_qspi_defconfig
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7
board/freescale/ls1012ardb/Makefile
Normal file
7
board/freescale/ls1012ardb/Makefile
Normal file
@ -0,0 +1,7 @@
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#
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# Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls1012ardb.o
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54
board/freescale/ls1012ardb/README
Normal file
54
board/freescale/ls1012ardb/README
Normal file
@ -0,0 +1,54 @@
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Overview
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--------
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QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
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development platform, with a complete debugging environment.
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The LS1012ARDB board supports the QorIQ LS1012A processor and is
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optimized to support the high-bandwidth DDR3L memory and
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a full complement of high-speed SerDes ports.
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LS1012A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
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SoC overview.
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LS1012ARDB board Overview
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-----------------------
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- SERDES Connections, 4 lanes supporting:
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- PCI Express - 3.0
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- SGMII, SGMII 2.5
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- SATA 3.0
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- DDR Controller
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- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
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signals to
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- QSPI NOR flash memory (2 virtual banks)
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- the QSPI emulator.s
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- USB 3.0
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- one high-speed USB 2.0/3.0 port.
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- Two enhanced secure digital host controllers:
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- SDHC1 controller can be connected to onboard SDHC connector
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- SDHC2 controller: Three dual 1:4 mux/demux devices,
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74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
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SDIO WiFi, SPI, and Ardiuno shield
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- 2 I2C controllers
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- One SATA onboard connectors
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- UART
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- The LS1012A processor consists of two UART controllers,
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out of which only UART1 is used on RDB.
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- ARM JTAG support
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Booting Options
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---------------
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a) QSPI Flash Emu Boot
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b) QSPI Flash 1
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c) QSPI Flash 2
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QSPI flash map
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--------------
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Images | Size |QSPI Flash Address
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------------------------------------------
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RCW + PBI | 1MB | 0x4000_0000
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U-boot | 1MB | 0x4010_0000
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U-boot Env | 1MB | 0x4020_0000
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PPA FIT image | 2MB | 0x4050_0000
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Linux ITB | ~53MB | 0x40A0_0000
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224
board/freescale/ls1012ardb/ls1012ardb.c
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224
board/freescale/ls1012ardb/ls1012ardb.c
Normal file
@ -0,0 +1,224 @@
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <environment.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
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{
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int timeout = 1000;
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out_be32(ptr, value);
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while (in_be32(ptr) & bits) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0)
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puts("Error: wait for clear timeout.\n");
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}
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int checkboard(void)
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{
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u8 in1;
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puts("Board: LS1012ARDB ");
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/* Initialize i2c early for Serial flash bank information */
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i2c_set_bus_num(0);
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if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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puts("Version");
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if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
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puts(": RevA");
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else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
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puts(": RevB");
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else
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puts(": unknown");
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printf(", boot from QSPI");
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if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
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puts(": emu\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
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puts(": bank1\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
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puts(": bank2\n");
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else
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puts("unknown\n");
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return 0;
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}
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void mmdc_init(void)
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{
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struct mmdc_p_regs *mmdc =
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(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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/* configure timing parms */
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out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
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out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
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out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
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out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
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/* other parms */
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out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
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out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
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out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
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out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
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/* out of reset delays */
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out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
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/* physical parms */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
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out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
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/* Enable MMDC */
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
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/* dram init sequence: update MRs */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
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CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
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/* dram init sequence: ZQCL */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
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CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
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FORCE_ZQ_AUTO_CALIBRATION);
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/* Calibrations now: wr lvl */
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
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CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
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set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
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mdelay(1);
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
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mdelay(1);
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/* Calibrations now: Read DQS gating calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
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set_wait_for_bits_clear(&mmdc->mpdgctrl0,
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AUTO_RD_DQS_GATING_CALIBRATION_EN,
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AUTO_RD_DQS_GATING_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* Calibrations now: Read calibration */
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
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set_wait_for_bits_clear(&mmdc->mprddlhwctl,
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AUTO_RD_CALIBRATION_EN,
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AUTO_RD_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3));
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/* PD, SR */
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out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
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out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
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/* refresh scheme */
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set_wait_for_bits_clear(&mmdc->mdref,
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CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
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START_REFRESH);
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/* disable CON_REQ */
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out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
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}
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int dram_init(void)
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{
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mmdc_init();
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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32
configs/ls1012ardb_qspi_defconfig
Normal file
32
configs/ls1012ardb_qspi_defconfig
Normal file
@ -0,0 +1,32 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1012ARDB=y
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_SPI_FLASH=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
107
include/configs/ls1012ardb.h
Normal file
107
include/configs/ls1012ardb.h
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __LS1012ARDB_H__
|
||||
#define __LS1012ARDB_H__
|
||||
|
||||
#include "ls1012a_common.h"
|
||||
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
|
||||
|
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
|
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C IO expander
|
||||
*/
|
||||
|
||||
#define I2C_MUX_IO1_ADDR 0x24
|
||||
#define __SW_BOOT_MASK 0xFC
|
||||
#define __SW_BOOT_EMU 0x10
|
||||
#define __SW_BOOT_BANK1 0x00
|
||||
#define __SW_BOOT_BANK2 0x01
|
||||
#define __SW_REV_MASK 0x07
|
||||
#define __SW_REV_A 0xF8
|
||||
#define __SW_REV_B 0xF0
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_MMC
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_SCSI
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_CMD_SCSI
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
|
||||
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
|
||||
|
||||
#define CONFIG_SYS_PCI_64BIT
|
||||
|
||||
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
|
||||
#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
|
||||
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
|
||||
#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
|
||||
|
||||
#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
|
||||
#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
|
||||
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
|
||||
#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
#endif /* __LS1012ARDB_H__ */
|
||||
Loading…
Reference in New Issue
Block a user