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* Patch by Ronen Shitrit, 10 Dec 2003:

Browse Source 
Add support for the Marvell DB64360 / DB64460 development boards

* Patch by Detlev Zundel, 10 Dec 2003:
  fix dependency problem in examples/Makefile
This commit is contained in:
wdenk 2004-01-03 00:43:19 +00:00
parent b6e4c4033c
commit 3a473b2a65
66 changed files with 30086 additions and 201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
CHANGELOG
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@ -2,6 +2,12 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patch by Ronen Shitrit, 10 Dec 2003:
Add support for the Marvell DB64360 / DB64460 development boards
* Patch by Detlev Zundel, 10 Dec 2003:
fix dependency problem in examples/Makefile
* Patch by Denis Peter, 8 Dec 2003
- add support for the PATI board (MPC555)
- add SPI support for the MPC5xx

4
MAKEALL
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@ -101,8 +101,8 @@ LIST_85xx=" \
#########################################################################
LIST_74xx=" \
EVB64260 P3G4 PCIPPC2 PCIPPC6 \
ZUMA \
DB64360 DB64460 EVB64260 P3G4 \
PCIPPC2 PCIPPC6 ZUMA \
"
LIST_7xx=" \

6
Makefile
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@ -863,6 +863,12 @@ AmigaOneG3SE_config: unconfig
BAB7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
DB64360_config: unconfig
@./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell
DB64460_config: unconfig
@./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
debris_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x debris etin

10
README
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@ -1,5 +1,5 @@
#
# (C) Copyright 2000 - 2002
# (C) Copyright 2000 - 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -197,6 +197,9 @@ Directory Hierarchy:
- board/ivm Files specific to IVMS8/IVML24 boards
- board/lantec Files specific to LANTEC boards
- board/lwmon Files specific to LWMON boards
- board/Marvell Files specific to Marvell development boards
- board/Marvell/db64360 Files specific to db64360 board
- board/Marvell/db64460 Files specific to db64460 board
- board/mbx8xx Files specific to MBX boards
- board/mpc8260ads
Files specific to MPC8260ADS and PQ2FADS-ZU boards
@ -365,8 +368,9 @@ The following options need to be configured:
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900,
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850
CONFIG_QS823, CONFIG_QS860T
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
CONFIG_QS823, CONFIG_QS860T, CONFIG_DB64360,
CONFIG_DB64460
ARM based boards:
-----------------

94
board/Marvell/common/bootseq.txt Normal file
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@ -0,0 +1,94 @@
(cpu/mpc7xxx/start.S)
start:
b boot_cold
start_warm:
b boot_warm
boot_cold:
boot_warm:
clear bats
init l2 (if enabled)
init altivec (if enabled)
invalidate l2 (if enabled)
setup bats (from defines in config_EVB)
enable_addr_trans: (if MMU enabled)
enable MSR_IR and MSR_DR
jump to in_flash
in_flash:
enable l1 dcache
gal_low_init: (board/evb64260/sdram_init.S)
config SDRAM (CFG, TIMING, DECODE)
init scratch regs (810 + 814)
detect DIMM0 (bank 0 only)
config SDRAM_PARA0 to 256/512Mbit
bl sdram_op_mode
detect bank0 width
write scratch reg 810
config SDRAM_PARA0 with results
config SDRAM_PARA1 with results
detect DIMM1 (bank 2 only)
config SDRAM_PARA2 to 256/512Mbit
detect bank2 width
write scratch reg 814
config SDRAM_PARA2 with results
config SDRAM_PARA3 with results
setup device bus timings/width
setup boot device timings/width
setup CPU_CONF (0x0)
setup cpu master control register 0x160
setup PCI0 TIMEOUT
setup PCI1 TIMEOUT
setup PCI0 BAR
setup PCI1 BAR
setup MPP control 0-3
setup GPP level control
setup Serial ports multiplex
setup stack pointer (r1)
setup GOT
call cpu_init_f
debug leds
board_init_f: (common/board.c)
board_pre_init:
remap gt regs?
map PCI mem/io
map device space
clear out interupts
init_timebase
env_init
serial_init
console_init_f
display_options
initdram: (board/evb64260/evb64260.c)
detect memory
for each bank:
dram_size()
setup PCI slave memory mappings
setup SCS
setup monitor
alloc board info struct
init bd struct
relocate_code: (cpu/mpc7xxx/start.S)
copy,got,clearbss
board_init_r(bd, dest_addr) (common/board.c)
setup bd function pointers
trap_init
flash_init: (board/evb64260/flash.c)
setup bd flash info
cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
nothing
mem_malloc_init
malloc_bin_reloc
spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
env_relocated
misc_init_r(bd): (board/evb64260/evb64260.c)
mpsc_init2

133
board/Marvell/common/ecctest.c Normal file
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@ -0,0 +1,133 @@
indent: Standard input:49: Warning:old style assignment ambiguity in "=*". Assuming "= *"
/*
* (C) Copyright 2001
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifdef ECC_TEST
static inline void ecc_off (void)
{
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
}
static inline void ecc_on (void)
{
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
}
static int putshex (const char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
printf ("%02x", buf[i]);
}
return 0;
}
static int char_memcpy (void *d, const void *s, int len)
{
int i;
char *cd = d;
const char *cs = s;
for (i = 0; i < len; i++) {
*(cd++) = *(cs++);
}
return 0;
}
static int memory_test (char *buf)
{
const char src[][16] = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
};
const int foo[] = { 0 };
int i, j, a;
printf ("\ntest @ %d %p\n", foo[0], buf);
for (i = 0; i < 12; i++) {
for (a = 0; a < 8; a++) {
const char *s = src[i] + a;
int align = (unsigned) (s) & 0x7;
/* ecc_off(); */
memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
/* ecc_off(); */
char_memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
}
}
return 0;
}
#endif

1072
board/Marvell/common/flash.c Normal file
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532
board/Marvell/common/i2c.c Normal file
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@ -0,0 +1,532 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
* extra improvments by Brain Waite
*/
#include <common.h>
#include <mpc8xx.h>
#include <malloc.h>
#include "../include/mv_gen_reg.h"
#include "../include/core.h"
#define MAX_I2C_RETRYS 10
#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
#undef DEBUG_I2C
/*#define DEBUG_I2C*/
#ifdef DEBUG_I2C
#define DP(x) x
#else
#define DP(x)
#endif
/* Assuming that there is only one master on the bus (us) */
static void i2c_init (int speed, int slaveaddr)
{
unsigned int n, m, freq, margin, power;
unsigned int actualN = 0, actualM = 0;
unsigned int control, status;
unsigned int minMargin = 0xffffffff;
unsigned int tclk = CFG_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
/* gtI2cMasterInit */
for (n = 0; n < 8; n++) {
for (m = 0; m < 16; m++) {
power = 2 << n; /* power = 2^(n+1) */
freq = tclk / (10 * (m + 1) * power);
if (i2cFreq > freq)
margin = i2cFreq - freq;
else
margin = freq - i2cFreq;
if (margin < minMargin) {
minMargin = margin;
actualN = n;
actualM = m;
}
}
}
DP (puts ("setup i2c bus\n"));
/* Setup bus */
/* gtI2cReset */
GT_REG_WRITE (I2C_SOFT_RESET, 0);
DP (puts ("udelay...\n"));
udelay (I2C_DELAY);
DP (puts ("set baudrate\n"));
GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
udelay (I2C_DELAY * 10);
DP (puts ("read control, baudrate\n"));
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
GT_REG_READ (I2C_CONTROL, &control);
}
static uchar i2c_start (void)
{ /* DB64360 checked -> ok */
unsigned int control, status;
int count = 0;
DP (puts ("i2c_start\n"));
/* Set the start bit */
/* gtI2cGenerateStartBit() */
GT_REG_READ (I2C_CONTROL, &control);
control |= (0x1 << 5); /* generate the I2C_START_BIT */
GT_REG_WRITE (I2C_CONTROL, control);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while ((status & 0xff) != 0x08) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
return (0);
}
static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
{
unsigned int status, data, bits = 7;
int count = 0;
DP (puts ("i2c_select_device\n"));
/* Output slave address */
if (ten_bit) {
bits = 10;
}
data = (dev_addr << 1);
/* set the read bit */
data |= read;
GT_REG_WRITE (I2C_DATA, data);
/* assert the address */
RESET_REG_BITS (I2C_CONTROL, BIT3);
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count = 0;
while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
if (bits == 10) {
printf ("10 bit I2C addressing not yet implemented\n");
return (0xff);
}
return (0);
}
static uchar i2c_get_data (uchar * return_data, int len)
{
unsigned int data, status;
int count = 0;
DP (puts ("i2c_get_data\n"));
while (len) {
/* Get and return the data */
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 5);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x50) {
udelay (I2C_DELAY);
if (count > 2) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return 0;
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_READ (I2C_DATA, &data);
len--;
*return_data = (uchar) data;
return_data++;
}
RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
while ((status & 0xff) != 0x58) {
udelay (I2C_DELAY);
if (count > 200) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
return (0);
}
static uchar i2c_write_data (unsigned int *data, int len)
{
unsigned int status;
int count = 0;
unsigned int temp;
unsigned int *temp_ptr = data;
DP (puts ("i2c_write_data\n"));
while (len) {
temp = (unsigned int) (*temp_ptr);
GT_REG_WRITE (I2C_DATA, temp);
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
/* 11-14-2002 Paul Marchese */
/* Can't have the write issuing a stop command */
/* it's wrong to have a stop bit in read stream or write stream */
/* since we don't know if it's really the end of the command */
/* or whether we have just send the device address + offset */
/* we will push issuing the stop command off to the original */
/* calling function */
/* set the interrupt bit in the control register */
GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 10);
return (0);
}
/* 11-14-2002 Paul Marchese */
/* created this function to get the i2c_write() */
/* function working properly. */
/* function to write bytes out on the i2c bus */
/* this is identical to the function i2c_write_data() */
/* except that it requires a buffer that is an */
/* unsigned character array. You can't use */
/* i2c_write_data() to send an array of unsigned characters */
/* since the byte of interest ends up on the wrong end of the bus */
/* aah, the joys of big endian versus little endian! */
/* */
/* returns 0 = success */
/* anything other than zero is failure */
static uchar i2c_write_byte (unsigned char *data, int len)
{
unsigned int status;
int count = 0;
unsigned int temp;
unsigned char *temp_ptr = data;
DP (puts ("i2c_write_byte\n"));
while (len) {
/* Set and assert the data */
temp = *temp_ptr;
GT_REG_WRITE (I2C_DATA, temp);
RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY);
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
while ((status & 0xff) != 0x28) {
udelay (I2C_DELAY);
if (count > 20) {
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
return (status);
}
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
count++;
}
len--;
temp_ptr++;
}
/* Can't have the write issuing a stop command */
/* it's wrong to have a stop bit in read stream or write stream */
/* since we don't know if it's really the end of the command */
/* or whether we have just send the device address + offset */
/* we will push issuing the stop command off to the original */
/* calling function */
/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
/* set the interrupt bit in the control register */
GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
udelay (I2C_DELAY * 10);
return (0);
}
static uchar
i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
int alen)
{
uchar status;
unsigned int table[2];
/* initialize the table of address offset bytes */
/* utilized for 2 byte address offsets */
/* NOTE: the order is high byte first! */
table[1] = offset & 0xff; /* low byte */
table[0] = offset / 0x100; /* high byte */
DP (puts ("i2c_set_dev_offset\n"));
status = i2c_select_device (dev_addr, 0, ten_bit);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to select device setting offset: 0x%02x\n",
status);
#endif
return status;
}
/* check the address offset length */
if (alen == 0)
/* no address offset */
return (0);
else if (alen == 1) {
/* 1 byte address offset */
status = i2c_write_data (&offset, 1);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else if (alen == 2) {
/* 2 bytes address offset */
status = i2c_write_data (table, 2);
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to write data: 0x%02x\n", status);
#endif
return status;
}
} else {
/* address offset unknown or not supported */
printf ("Address length offset %d is not supported\n", alen);
return 1;
}
return 0; /* sucessful completion */
}
uchar
i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
DP (puts ("i2c_read\n"));
i2c_init (i2cFreq, 0); /* set the i2c frequency */
status = i2c_start ();
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
i2c_init (i2cFreq, 0); /* set the i2c frequency again */
status = i2c_start ();
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction restart failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */
if (status) {
#ifdef DEBUG_I2C
printf ("Address not acknowledged: 0x%02x\n", status);
#endif
return status;
}
status = i2c_get_data (data, len);
if (status) {
#ifdef DEBUG_I2C
printf ("Data not recieved: 0x%02x\n", status);
#endif
return status;
}
return 0;
}
/* 11-14-2002 Paul Marchese */
/* Function to set the I2C stop bit */
void i2c_stop (void)
{
GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
}
/* 11-14-2002 Paul Marchese */
/* I2C write function */
/* dev_addr = device address */
/* offset = address offset */
/* alen = length in bytes of the address offset */
/* data = pointer to buffer to read data into */
/* len = # of bytes to read */
/* */
/* returns 0 = succesful */
/* anything but zero is failure */
uchar
i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
DP (puts ("i2c_write\n"));
i2c_init (i2cFreq, 0); /* set the i2c frequency */
status = i2c_start (); /* send a start bit */
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return status;
}
status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address & offset: 0x%02x\n",
status);
#endif
return status;
}
status = i2c_write_byte (data, len); /* write the data */
if (status) {
#ifdef DEBUG_I2C
printf ("Data not written: 0x%02x\n", status);
#endif
return status;
}
/* issue a stop bit */
i2c_stop ();
return 0;
}
/* 11-14-2002 Paul Marchese */
/* function to determine if an I2C device is present */
/* chip = device address of chip to check for */
/* */
/* returns 0 = sucessful, the device exists */
/* anything other than zero is failure, no device */
int i2c_probe (uchar chip)
{
/* We are just looking for an <ACK> back. */
/* To see if the device/chip is there */
#ifdef DEBUG_I2C
unsigned int i2c_status;
#endif
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
DP (puts ("i2c_probe\n"));
i2c_init (i2cFreq, 0); /* set the i2c frequency */
status = i2c_start (); /* send a start bit */
if (status) {
#ifdef DEBUG_I2C
printf ("Transaction start failed: 0x%02x\n", status);
#endif
return (int) status;
}
status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
if (status) {
#ifdef DEBUG_I2C
printf ("Failed to set slave address: 0x%02x\n", status);
#endif
return (int) status;
}
#ifdef DEBUG_I2C
GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
printf ("address %#x returned %#x\n", chip, i2c_status);
#endif
/* issue a stop bit */
i2c_stop ();
return 0; /* successful completion */
}

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
*/
#ifndef __I2C_H__
#define __I2C_H__
/* function declarations */
uchar i2c_read(uchar, unsigned int, int, uchar*, int);
#endif

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for the marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*/
#include <common.h>
#include <mpc8xx.h>
#include "../include/mv_gen_reg.h"
#include "../include/memory.h"
#include "intel_flash.h"
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
static void bank_reset (flash_info_t * info, int sect)
{
bank_addr_t addrw, eaddrw;
addrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (addrw);
while (addrw < eaddrw) {
#ifdef FLASH_DEBUG
printf (" writing reset cmd to addr 0x%08lx\n",
(unsigned long) addrw);
#endif
*addrw = BANK_CMD_RST;
addrw++;
}
}
static void bank_erase_init (flash_info_t * info, int sect)
{
bank_addr_t addrw, saddrw, eaddrw;
int flag;
#ifdef FLASH_DEBUG
printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
#endif
saddrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
#ifdef FLASH_DEBUG
printf ("erasing sector %d, start addr = 0x%08lx "
"(bank next word addr = 0x%08lx)\n", sect,
(unsigned long) saddrw, (unsigned long) eaddrw);
#endif
/* Disable intrs which might cause a timeout here */
flag = disable_interrupts ();
for (addrw = saddrw; addrw < eaddrw; addrw++) {
#ifdef FLASH_DEBUG
printf (" writing erase cmd to addr 0x%08lx\n",
(unsigned long) addrw);
#endif
*addrw = BANK_CMD_ERASE1;
*addrw = BANK_CMD_ERASE2;
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
}
static int bank_erase_poll (flash_info_t * info, int sect)
{
bank_addr_t addrw, saddrw, eaddrw;
int sectdone, haderr;
saddrw = (bank_addr_t) info->start[sect];
eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
sectdone = 1;
haderr = 0;
for (addrw = saddrw; addrw < eaddrw; addrw++) {
bank_word_t stat = *addrw;
#ifdef FLASH_DEBUG
printf (" checking status at addr "
"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
#endif
if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
sectdone = 0;
else if ((stat & BANK_STAT_ERR) != 0) {
printf (" failed on sector %d "
"(stat = 0x%08x) at "
"address 0x%p\n", sect, stat, addrw);
*addrw = BANK_CMD_CLR_STAT;
haderr = 1;
}
}
if (haderr)
return (-1);
else
return (sectdone);
}
int write_word_intel (bank_addr_t addr, bank_word_t value)
{
bank_word_t stat;
ulong start;
int flag, retval;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = BANK_CMD_PROG;
*addr = value;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
retval = 0;
/* data polling for D7 */
start = get_timer (0);
do {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
retval = 1;
goto done;
}
stat = *addr;
} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
if ((stat & BANK_STAT_ERR) != 0) {
printf ("flash program failed (stat = 0x%08lx) "
"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
*addr = BANK_CMD_CLR_STAT;
retval = 3;
}
done:
/* reset to read mode */
*addr = BANK_CMD_RST;
return (retval);
}
/*-----------------------------------------------------------------------
*/
int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
{
int prot, sect, haderr;
ulong start, now, last;
#ifdef FLASH_DEBUG
printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
" Bank # %d: ", s_last - s_first + 1, s_first, s_last,
(info - flash_info) + 1);
flash_print_info (info);
#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
}
start = get_timer (0);
last = 0;
haderr = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
ulong estart;
int sectdone;
bank_erase_init (info, sect);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
estart = get_timer (start);
do {
now = get_timer (start);
if (now - estart > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout (sect %d)\n", sect);
haderr = 1;
break;
}
#ifndef FLASH_DEBUG
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
#endif
sectdone = bank_erase_poll (info, sect);
if (sectdone < 0) {
haderr = 1;
break;
}
} while (!sectdone);
if (haderr)
break;
}
}
if (haderr > 0)
printf (" failed\n");
else
printf (" done\n");
/* reset to read mode */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
bank_reset (info, sect);
}
}
return haderr;
}

186
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Hacked for the marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*/
/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
/*
* acceptable chips types are:
*
* 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
*/
/* register addresses, valid only following an CHIP_CMD_RD_ID command */
#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
/* Commands */
#define CHIP_CMD_RST 0xFF /* reset flash */
#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
#define CHIP_CMD_PROG 0x40 /* program word command */
#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
/* status register bits */
#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
#define CHIP_STAT_VPPS 0x08 /* VPP Status */
#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
/* ID and Lock Configuration */
#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
#define CHIP_RD_ID_DEV CFG_FLASH_ID
/* dimensions */
#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
#define CHIP_NBLOCKS 128
#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
/********************** DEFINES for Hymod Flash ******************************/
/*
* The hymod board has 2 x 28F320J5 chips running in
* 16 bit mode, for a 32 bit wide bank.
*/
typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
typedef volatile bank_word_t *bank_addr_t;
typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
#define BANK_NBLOCKS CHIP_NBLOCKS
#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
#define MAX_BANKS 1 /* only one bank possible */
/* align bank addresses and sizes to bank word boundaries */
#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
& ~(BANK_WIDTH - 1)))
#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
(bank_size_t)(s) + (BANK_WIDTH - 1)))
/* align bank addresses and sizes to bank block boundaries */
#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
& ~(BANK_BLKSZ - 1)))
#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
(bank_size_t)(s) + (BANK_BLKSZ - 1)))
/* align bank addresses and sizes to bank boundaries */
#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
& ~(BANK_SIZE - 1)))
#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
(bank_size_t)(s) + (BANK_SIZE - 1)))
/* add an offset to a bank address */
#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
(bank_size_t)(o))
/* get base address of bank b, given flash base address a */
#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
(bank_size_t)(b) * BANK_SIZE)
/* adjust a bank address to start of next word, block or bank */
#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
BANK_WIDTH)
#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
BANK_BLKSZ)
#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
BANK_SIZE)
/* get bank address of chip register r given a bank base address a */
#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
((bank_size_t)(r) << BANK_WSHIFT))
/* make a bank address for each chip register address */
#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
/*
* replicate a chip cmd/stat/rd value into each byte position within a word
* so that multiple chips are accessed in a single word i/o operation
*
* this must be as wide as the bank_word_t type, and take into account the
* chip width and bank layout
*/
#define BANK_FILL_WORD(o) ((bank_word_t)(o))
/* make a bank word value for each chip cmd/stat/rd value */
/* Commands */
#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
/* status register bits */
#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
/* ID and Lock Configuration */
#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)

1390
board/Marvell/common/memory.c Normal file
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235
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#include <config.h>
#include <74xx_7xx.h>
#include "version.h"
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "../include/mv_gen_reg.h"
#ifdef CONFIG_ECC
/* Galileo specific asm code for initializing ECC */
.globl board_relocate_rom
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
lis r11, CFG_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
mtlr r7
blr
.globl board_init_ecc
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
* which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
lis r8, CFG_MONITOR_LEN@h
ori r8, r8, CFG_MONITOR_LEN@l
divw r3, r10, r8
/* set up the counter, and init the starting address */
mtctr r3
li r12, 0
/* bytes per transfer */
mr r5, r8
about_to_init_ecc:
1: mr r3, r12
mr r4, r12
bl start_idma_transfer_0
bl wait_for_idma_0
bl stop_idma_engine_0
add r12, r12, r8
bdnz 1b
mtlr r7
blr
/* r3: dest addr
* r4: source addr
* r5: byte count
* r11: gt regbase
* trashes: r6, r5
*/
start_idma_transfer_0:
/* set the byte count, including the OWN bit */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
stwbrx r5, 0, (r6)
/* set the source address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
stwbrx r4, 0, (r6)
/* set the dest address */
mr r6, r11
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
stwbrx r3, 0, (r6)
/* set the next record pointer */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
stwbrx r5, 0, (r6)
/* set the low control register */
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
bit 12 is channel enable */
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
/* 15 shifted by 16 (oris) == bit 31 */
oris r5, r5, (1 << 15)
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
/* this waits for the bytecount to return to zero, indicating
* that the trasfer is complete */
wait_for_idma_0:
mr r5, r11
lis r6, 0xff
ori r6, r6, 0xffff
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
1: lwbrx r4, 0, (r5)
and. r4, r4, r6
bne 1b
blr
/* this turns off channel 0 of the idma engine */
stop_idma_engine_0:
/* shut off the DMA engine */
li r5, 0
mr r6, r11
ori r6, r6, CHANNEL0CONTROL
stwbrx r5, 0, (r6)
blr
#endif
#ifdef CFG_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
lis r3, CFG_DFL_GT_REGS@h
ori r3, r3, CFG_DFL_GT_REGS@l
lis r4, CFG_GT_REGS@h
ori r4, r4, CFG_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
lwbrx r6, r5, r4
andi. r6, r6, 0xffff
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
/* rlwinm r7, r4, 8, 16, 31
rlwinm r7, r4, 12, 16, 31 */ /* original */
rlwinm r7, r4, 16, 16, 31
/* -----------------------------------------------------*/
cmp cr0, r7, r6
beqlr
/* nope, have to move the registers */
lwbrx r6, r5, r3
andis. r6, r6, 0xffff
or r6, r6, r7
stwbrx r6, r5, r3
/* now, poll for the change */
1: lwbrx r7, r5, r4
cmp cr0, r7, r6
bne 1b
/* done! */
blr
#endif
/* For use of the debug LEDs */
.global led_on0_relocated
led_on0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC80
ori r18, r18, 0x8000
stw r21, 0x0(r18)
/* stw r18, 0x0(r18) */
sync
blr
.global led_off0_relocated
led_off0_relocated:
xor r21, r21, r21
xor r18, r18, r18
lis r18, 0xFC81
ori r18, r18, 0x4000
stw r21, 0x0(r18)
/* stw r18, 0x0(r18) */
sync
blr
.global led_on0
led_on0:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0x8000
stw r18, 0x0(r18)
sync
blr
.global led_off0
led_off0:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x4000
stw r18, 0x0(r18)
sync
blr
.global led_on1
led_on1:
xor r18, r18, r18
lis r18, 0x1c80
ori r18, r18, 0xc000
stw r18, 0x0(r18)
sync
blr
.global led_off1
led_off1:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x8000
stw r18, 0x0(r18)
sync
blr
.global led_on2
led_on2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0x0000
stw r18, 0x0(r18)
sync
blr
.global led_off2
led_off2:
xor r18, r18, r18
lis r18, 0x1c81
ori r18, r18, 0xc000
stw r18, 0x0(r18)
sync
blr

66
board/Marvell/common/ns16550.c Normal file
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/*
* COM1 NS16550 support
* originally from linux source (arch/ppc/boot/ns16550.c)
* modified to use CFG_ISA_MEM and new defines
*
* further modified by Josh Huber <huber@mclx.com> to support
* the DUART on the Galileo Eval board. (db64360)
*/
#include <config.h>
#include "ns16550.h"
#ifdef ZUMA_NTL
/* no 16550 device */
#else
const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
(NS16550_t) (CFG_DUART_IO + 0x20)
};
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
{
volatile struct NS16550 *com_port;
com_port = (struct NS16550 *) COM_PORTS[chan];
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
/* Clear & enable FIFOs */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
return (com_port);
}
void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
/* Clear & enable FIFOs */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
}
void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
{
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = c;
}
unsigned char NS16550_getc (volatile struct NS16550 *com_port)
{
while ((com_port->lsr & LSR_DR) == 0);
return (com_port->rbr);
}
int NS16550_tstc (volatile struct NS16550 *com_port)
{
return ((com_port->lsr & LSR_DR) != 0);
}
#endif

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/*
* NS16550 Serial Port
* originally from linux source (arch/ppc/boot/ns16550.h)
* modified slightly to
* have addresses as offsets from CFG_ISA_BASE
* added a few more definitions
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* further modified to support the DUART in the Galileo eval board
* modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*/
#ifndef __NS16550_H__
#define __NS16550_H__
/* the padding is necessary because on the galileo board the UART is
wired in with the 3 address lines shifted over by 2 bits */
struct NS16550
{
unsigned char rbr; /* 0 = 0-3*/
int pad1:24;
unsigned char ier; /* 1 = 4-7*/
int pad2:24;
unsigned char fcr; /* 2 = 8-b*/
int pad3:24;
unsigned char lcr; /* 3 = c-f*/
int pad4:24;
unsigned char mcr; /* 4 = 10-13*/
int pad5:24;
unsigned char lsr; /* 5 = 14-17*/
int pad6:24;
unsigned char msr; /* 6 =18-1b*/
int pad7:24;
unsigned char scr; /* 7 =1c-1f*/
int pad8:24;
} __attribute__ ((packed));
/* aliases */
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier
#define FCR_FIFO_EN 0x01 /*fifo enable*/
#define FCR_RXSR 0x02 /*reciever soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_DMA_EN 0x04
#define MCR_TX_DFR 0x08
#define LCR_WLS_MSK 0x03 /* character length slect mask*/
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble*/
#define LCR_EPS 0x10 /* Even Parity Select*/
#define LCR_STKP 0x20 /* Stick Parity*/
#define LCR_SBRK 0x40 /* Set Break*/
#define LCR_BKSE 0x80 /* Bank select enable*/
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
/* useful defaults for LCR*/
#define LCR_8N1 0x03
#define COM1 0x03F8
#define COM2 0x02F8
volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
unsigned char NS16550_getc(volatile struct NS16550 *com_port);
int NS16550_tstc(volatile struct NS16550 *com_port);
void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
typedef struct NS16550 *NS16550_t;
extern const NS16550_t COM_PORTS[];
#endif

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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
*/
#ifndef _MV_PPC_ERRNO_H
#define _MV_PPC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Arg list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK 58 /* File locking deadlock error */
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
/* Should never be seen by user programs */
#define ERESTARTSYS 512
#define ERESTARTNOINTR 513
#define ERESTARTNOHAND 514 /* restart if no handler.. */
#define ENOIOCTLCMD 515 /* No ioctl command */
#define _LAST_ERRNO 515
#endif

178
board/Marvell/common/serial.c Normal file
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* modified for marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* serial.c - serial support for the gal ev board
*/
/* supports both the 16650 duart and the MPSC */
#include <common.h>
#include <command.h>
#include "../include/memory.h"
#include "serial.h"
#ifdef CONFIG_DB64360
#include "../db64360/mpsc.h"
#endif
#ifdef CONFIG_DB64460
#include "../db64460/mpsc.h"
#endif
#include "ns16550.h"
#ifdef CONFIG_MPSC
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
int clock_divisor = 230400 / gd->baudrate;
#endif
mpsc_init (gd->baudrate);
/* init the DUART chans so that KGDB in the kernel can use them */
#ifdef CFG_INIT_CHAN1
NS16550_reinit (COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
NS16550_reinit (COM_PORTS[1], clock_divisor);
#endif
return (0);
}
void serial_putc (const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
int serial_getc (void)
{
return mpsc_getchar ();
}
int serial_tstc (void)
{
return mpsc_test_char ();
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
#else /* ! CONFIG_MPSC */
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
(void) NS16550_init (0, clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
(void) NS16550_init (1, clock_divisor);
#endif
return (0);
}
void serial_putc (const char c)
{
if (c == '\n')
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
}
int serial_getc (void)
{
return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
}
int serial_tstc (void)
{
return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
NS16550_reinit (COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
NS16550_reinit (COM_PORTS[1], clock_divisor);
#endif
}
#endif /* CONFIG_MPSC */
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
void kgdb_serial_init (void)
{
}
void putDebugChar (int c)
{
serial_putc (c);
}
void putDebugStr (const char *str)
{
serial_puts (str);
}
int getDebugChar (void)
{
return serial_getc ();
}
void kgdb_interruptible (int yes)
{
return;
}
#endif /* CFG_CMD_KGDB */

89
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* modified for marvell db64360 eval board by
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* serial.h - mostly useful for DUART serial_init in serial.c */
#ifndef __SERIAL_H__
#define __SERIAL_H__
#if 0
#define B230400 1
#define B115200 2
#define B57600 4
#define B38400 82
#define B19200 163
#define B9600 24
#define B4800 651
#define B2400 1302
#define B1200 2604
#define B600 5208
#define B300 10417
#define B150 20833
#define B110 28409
#define BDEFAULT B115200
/* this stuff is important to initialize
the DUART channels */
#define Scale 0x01L /* distance between port addresses */
#define COM1 0x000003f8 /* Keyboard */
#define COM2 0x000002f8 /* Host */
/* Port Definitions relative to base COM port addresses */
#define DataIn (0x00*Scale) /* data input port */
#define DataOut (0x00*Scale) /* data output port */
#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
#define Ier (0x01*Scale) /* interrupt enable register */
#define Iir (0x02*Scale) /* interrupt identification register */
#define Lcr (0x03*Scale) /* line control register */
#define Mcr (0x04*Scale) /* modem control register */
#define Lsr (0x05*Scale) /* line status register */
#define Msr (0x06*Scale) /* modem status register */
/* Bit Definitions for above ports */
#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
#define McrDflt (McrRts|McrDtr)
#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
/* b6: transmitter empty */
#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
#define IerRda 0xf /* b0: Enable received data available interrupt */
#endif
#endif /* __SERIAL_H__ */

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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* main board support/init for the Galileo Eval board DB64360.
*/
#ifndef __64360_H__
#define __64360_H__
/* CPU Configuration bits */
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
#define CPU_CONF_SINGLE_CPU (1 << 11)
#define CPU_CONF_ENDIANESS (1 << 12)
#define CPU_CONF_PIPELINE (1 << 13)
#define CPU_CONF_STOP_RETRY (1 << 17)
#define CPU_CONF_MULTI_DECODE (1 << 18)
#define CPU_CONF_DP_VALID (1 << 19)
#define CPU_CONF_PERR_PROP (1 << 22)
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
#define CPU_CONF_AP_VALID (1 << 26)
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
/* CPU Master Control bits */
#define CPU_MAST_CTL_ARB_EN (1 << 8)
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
#endif /* __64360_H__ */

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#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
SOBJS = ../common/misc.o
OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

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#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# EVB64360 boards
#
TEXT_BASE = 0xfff00000

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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
*/
/*
* db64360.c - main board support/init for the Galileo Eval board.
*/
#include <common.h>
#include <74xx_7xx.h>
#include "../include/memory.h"
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
#include "64360.h"
#include "mv_regs.h"
#undef DEBUG
/*#define DEBUG */
#define MAP_PCI
#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
* board_pre_init wont work right (like in cpu_init_f).
* See also my_remap_gt_regs below. (NTL)
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
/*
* This is a version of the GT register space remapping function that
* doesn't touch globals (meaning, it's ok to run from flash.)
*
* Unfortunately, this has the side effect that a writable
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
*/
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
{
u32 temp;
/* check and see if it's already moved */
/* original ppcboot 1.1.6 source
temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 20)
return;
temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 20);
out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
original ppcboot 1.1.6 source end */
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
}
#ifdef CONFIG_PCI
static void gt_pci_config (void)
{
unsigned int stat;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
* config registers by writing ones to the bus and device.
* We then update the Virtual register with the correct value for the bus and device.
*/
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
}
/* Enable master */
PCI_MASTER_ENABLE (0, SELF);
PCI_MASTER_ENABLE (1, SELF);
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
<<
18);
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
/* ronen - enable only CS0 and Internal reg!! */
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
/*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CFG_GT_REGS);
#endif
}
#endif
/* Setup CPU interface paramaters */
static void gt_cpu_config (void)
{
cpu_t cpu = get_cpu_type ();
ulong tmp;
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64360 P.399 */
#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
tmp |= CPU_CONF_DP_VALID;
tmp |= CPU_CONF_AP_VALID;
tmp |= CPU_CONF_PIPELINE;
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
/* CPU master control register */
tmp = GTREGREAD (CPU_MASTER_CONTROL);
tmp |= CPU_MAST_CTL_ARB_EN;
if ((cpu == CPU_7400) ||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
tmp |= CPU_MAST_CTL_CLEAN_BLK;
tmp |= CPU_MAST_CTL_FLUSH_BLK;
} else {
/* cleanblock must be cleared for CPUs
* that do not support this command (603e, 750)
* see Res#1 */
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
}
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
}
/*
* board_pre_init.
*
* set up gal. device mappings, etc.
*/
int board_pre_init (void)
{
uchar sram_boot = 0;
/*
* set up the GT the way the kernel wants it
* the call to move the GT register space will obviously
* fail if it has already been done, but we're going to assume
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
gt_pci_config ();
#endif
/* mask all external interrupt sources */
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
/* new in MV6436x */
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
/* --------------------- */
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
/* does not exist in MV6436x
GT_REG_WRITE(CPU_INT_0_MASK, 0);
GT_REG_WRITE(CPU_INT_1_MASK, 0);
GT_REG_WRITE(CPU_INT_2_MASK, 0);
GT_REG_WRITE(CPU_INT_3_MASK, 0);
--------------------- */
/* ----- DEVICE BUS SETTINGS ------ */
/*
* EVB
* 0 - SRAM ????
* 1 - RTC ????
* 2 - UART ????
* 3 - Flash checked 32Bit Intel Strata
* boot - BootCS checked 8Bit 29LV040B
*
* Zuma
* 0 - Flash
* boot - BootCS
*/
/*
* the dual 7450 module requires burst access to the boot
* device, so the serial rom copies the boot device to the
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
/* configure device timing */
#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
#endif
#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
#endif
#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
#endif
#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CFG_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
return 0;
}
/* various things to do after relocation */
int misc_init_r ()
{
icache_enable ();
#ifdef CFG_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
mpsc_sdma_init ();
mpsc_init2 ();
#endif
#if 0
/* disable the dcache and MMU */
dcache_lock ();
#endif
return 0;
}
void after_reloc (ulong dest_addr, gd_t * gd)
{
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* right now, assume borad type. (there is just one...after all)
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
/* utility functions */
void debug_led (int led, int mode)
{
volatile int *addr = 0;
int dummy;
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x1c000);
break;
}
}
dummy = *addr;
}
int display_mem_map (void)
{
int i, j;
unsigned int base, size, width;
/* SDRAM */
printf ("SD (DDR) RAM\n");
for (i = 0; i <= BANK3; i++) {
base = memoryGetBankBaseAddress (i);
size = memoryGetBankSize (i);
if (size != 0) {
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
i, base, size >> 20);
}
}
/* CPU's PCI windows */
for (i = 0; i <= PCI_HOST1; i++) {
printf ("\nCPU's PCI %d windows\n", i);
base = pciGetSpaceBase (i, PCI_IO);
size = pciGetSpaceSize (i, PCI_IO);
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
size >> 20);
for (j = 0;
j <=
PCI_REGION0
/*ronen currently only first PCI MEM is used 3 */ ;
j++) {
base = pciGetSpaceBase (i, j);
size = pciGetSpaceSize (i, j);
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
}
}
/* Devices */
printf ("\nDEVICES\n");
for (i = 0; i <= DEVICE3; i++) {
base = memoryGetDeviceBaseAddress (i);
size = memoryGetDeviceSize (i);
width = memoryGetDeviceWidth (i) * 8;
printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
if (i == 0)
printf ("\t- EXT SRAM (actual - 1M)\n");
else if (i == 1)
printf ("\t- RTC\n");
else if (i == 2)
printf ("\t- UART\n");
else
printf ("\t- LARGE FLASH\n");
}
/* Bootrom */
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
size = memoryGetDeviceSize (BOOT_DEVICE);
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
base, size >> 20, width);
return (0);
}
/* DRAM check routines copied from gw8260 */
#if defined (CFG_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
/* */
/* DESCRIPTION: */
/* this function performs a double word move from the data at */
/* the source pointer to the location at the destination pointer. */
/* */
/* INPUTS: */
/* unsigned long long *src - pointer to data to move */
/* */
/* OUTPUTS: */
/* unsigned long long *dest - pointer to locate to move data */
/* */
/* RETURNS: */
/* None */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CFG_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaa,
0xcccccccccccccccc,
0xf0f0f0f0f0f0f0f0,
0xff00ff00ff00ff00,
0xffff0000ffff0000,
0xffffffff00000000,
0x00000000ffffffff,
0x0000ffff0000ffff,
0x00ff00ff00ff00ff,
0x0f0f0f0f0f0f0f0f,
0x3333333333333333,
0x5555555555555555
};
/*********************************************************************/
/* NAME: mem_test_data() - test data lines for shorts and opens */
/* */
/* DESCRIPTION: */
/* Tests data lines for shorts and opens by forcing adjacent data */
/* to opposite states. Because the data lines could be routed in */
/* an arbitrary manner the must ensure test patterns ensure that */
/* every case is tested. By using the following series of binary */
/* patterns every combination of adjacent bits is test regardless */
/* of routing. */
/* */
/* ...101010101010101010101010 */
/* ...110011001100110011001100 */
/* ...111100001111000011110000 */
/* ...111111110000000011111111 */
/* */
/* Carrying this out, gives us six hex patterns as follows: */
/* */
/* 0xaaaaaaaaaaaaaaaa */
/* 0xcccccccccccccccc */
/* 0xf0f0f0f0f0f0f0f0 */
/* 0xff00ff00ff00ff00 */
/* 0xffff0000ffff0000 */
/* 0xffffffff00000000 */
/* */
/* The number test patterns will always be given by: */
/* */
/* log(base 2)(number data bits) = log2 (64) = 6 */
/* */
/* To test for short and opens to other signals on our boards. we */
/* simply */
/* test with the 1's complemnt of the paterns as well. */
/* */
/* OUTPUTS: */
/* Displays failing test pattern */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
unsigned long long temp64;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_DATA */
#if defined (CFG_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
/* DESCRIPTION: */
/* This function performs a test to verify that each word im */
/* memory is uniquly addressable. The test sequence is as follows: */
/* */
/* 1) write the address of each word to each word. */
/* 2) verify that each location equals its address */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CFG_MEMTEST_START;
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
for (i = 0; i < size; i++) {
pmem[i] = i;
}
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
#if defined (CFG_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
/* DESCRIPTION: */
/* Marches up through memory. At each location verifies rmask if */
/* read = 1. At each location write wmask if write = 1. Displays */
/* failing address and pattern. */
/* */
/* INPUTS: */
/* volatile unsigned long long * base - start address of test */
/* unsigned int size - number of dwords(64-bit) to test */
/* unsigned long long rmask - read verify mask */
/* unsigned long long wmask - wrtie verify mask */
/* short read - verifies rmask if read = 1 */
/* short write - writes wmask if write = 1 */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
{
unsigned int i;
unsigned long long temp;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *) &(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
return 1;
}
}
if (write != 0) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *) &(base[i]));
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
/* */
/* DESCRIPTION: */
/* Performs a walking ones through entire physical memory. The */
/* test uses as series of memory marches, mem_march(), to verify */
/* and write the test patterns to memory. The test sequence is as */
/* follows: */
/* 1) march writing 0000...0001 */
/* 2) march verifying 0000...0001 , writing 0000...0010 */
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
/* the write mask equals 1000...0000 */
/* 4) march verifying 1000...0000 */
/* The test fails if any of the memory marches return a failure. */
/* */
/* OUTPUTS: */
/* Displays which pass on the memory test is executing */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CFG_MEMTEST_START;
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
unsigned int i;
mask = 0x01;
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2);
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf ("\b\b\b\b\b\b\b");
}
printf ("Last Pass");
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
/*********************************************************************/
/* NAME: testdram() - calls any enabled memory tests */
/* */
/* DESCRIPTION: */
/* Runs memory tests if the environment test variables are set to */
/* 'y'. */
/* */
/* INPUTS: */
/* testdramdata - If set to 'y', data test is run. */
/* testdramaddress - If set to 'y', address test is run. */
/* testdramwalk - If set to 'y', walking ones test is run */
/* */
/* OUTPUTS: */
/* None */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int testdram (void)
{
char *s;
int rundata, runaddress, runwalk;
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("passed\n");
}
return 0;
}
#endif /* CFG_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
/* the kernel data areas. */
/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
new_loc |
(INTERNAL_SPACE_DECODE)))))
!= temp);
}
void board_prebootm_init ()
{
/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
/* Stop GigE Rx DMA engines */
GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
/* Relocate MV64360 internal regs */
my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
invalidate_l1_instruction_cache ();
flush_data_cache ();
dcache_disable ();
}

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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __EVB64360_ETH_H__
#define __EVB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
int db64360_eth0_poll(void);
int db64360_eth0_transmit(unsigned int s, volatile char *p);
void db64360_eth0_disable(void);
bool network_start(bd_t *bis);
#endif /* __EVB64360_ETH_H__ */

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/*
* (C) Copyright 2001
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
*
************************************************************************/
/*
* mpsc.h - header file for MPSC in uart mode (console driver)
*/
#ifndef __MPSC_H__
#define __MPSC_H__
/* include actual Galileo defines */
#include "../include/mv_gen_reg.h"
/* driver related defines */
int mpsc_init(int baud);
void mpsc_sdma_init(void);
void mpsc_init2(void);
int galbrg_set_baudrate(int channel, int rate);
int mpsc_putchar_early(char ch);
char mpsc_getchar_debug(void);
int mpsc_test_char_debug(void);
int mpsc_test_char_sdma(void);
extern int (*mpsc_putchar)(char ch);
extern char (*mpsc_getchar)(void);
extern int (*mpsc_test_char)(void);
#define CHANNEL CONFIG_MPSC_PORT
#define TX_DESC 5
#define RX_DESC 20
#define DESC_FIRST 0x00010000
#define DESC_LAST 0x00020000
#define DESC_OWNER_BIT 0x80000000
#define TX_DEMAND 0x00800000
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)
/* MPSC defines */
#define GALMPSC_CONNECT 0x1
#define GALMPSC_DISCONNECT 0x0
#define GALMPSC_UART 0x1
#define GALMPSC_STOP_BITS_1 0x0
#define GALMPSC_STOP_BITS_2 0x1
#define GALMPSC_CHAR_LENGTH_8 0x3
#define GALMPSC_CHAR_LENGTH_7 0x2
#define GALMPSC_PARITY_ODD 0x0
#define GALMPSC_PARITY_EVEN 0x2
#define GALMPSC_PARITY_MARK 0x3
#define GALMPSC_PARITY_SPACE 0x1
#define GALMPSC_PARITY_NONE -1
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
#define GALMPSC_REG_GAP 0x1000
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
#define GALSDMA_COMMAND_FIRST (1 << 16)
#define GALSDMA_COMMAND_LAST (1 << 17)
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
#define GALSDMA_COMMAND_AUTO (1 << 30)
#define GALSDMA_COMMAND_OWNER (1 << 31)
#define GALSDMA_RX 0
#define GALSDMA_TX 1
/* CHANNEL2 should be CHANNEL1, according to documentation,
* but to work with the current GTREGS file...
*/
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
#define GALSDMA_REG_DIFF 0x2000
/* WRONG in gt64260R.h */
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
#define GALMPSC_0_INT_CAUSE 0xb804
#define GALMPSC_0_INT_MASK 0xb884
#define GALSDMA_MODE_UART 0
#define GALSDMA_MODE_BISYNC 1
#define GALSDMA_MODE_HDLC 2
#define GALSDMA_MODE_TRANSPARENT 3
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
#define GALBRG_REG_GAP 0x0008
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
#endif /* __MPSC_H__ */

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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mv_eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __DB64360_ETH_H__
#define __DB64360_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
#include <net.h>
#include "mv_regs.h"
#include "../common/ppc_error_no.h"
/*************************************************************************
**************************************************************************
**************************************************************************
* The first part is the high level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#endif
/* Port attributes */
/*#define MAX_RX_QUEUE_NUM 8*/
/*#define MAX_TX_QUEUE_NUM 8*/
#define MAX_RX_QUEUE_NUM 1
#define MAX_TX_QUEUE_NUM 1
/* Use one TX queue and one RX queue */
#define MV64360_TX_QUEUE_NUM 1
#define MV64360_RX_QUEUE_NUM 1
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 10 descriptors */
#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
#else
#define MV64360_TX_QUEUE_SIZE 4
#endif
/* Default RX ring size is 4 descriptors */
#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
#else
#define MV64360_RX_QUEUE_SIZE 4
#endif
#ifdef CONFIG_RX_BUFFER_SIZE
#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
#else
#define MV64360_RX_BUFFER_SIZE 1600
#endif
#ifdef CONFIG_TX_BUFFER_SIZE
#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
#else
#define MV64360_TX_BUFFER_SIZE 1600
#endif
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
/* Private data structure used for ethernet device */
struct mv64360_eth_priv {
unsigned int port_num;
struct net_device_stats *stats;
/* to buffer area aligned */
char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
/* Size of Tx Ring per queue */
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
/* Size of Rx Ring per queue */
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
/* Magic Number for Ethernet running */
unsigned int eth_running;
};
int mv64360_eth_init (struct eth_device *dev);
int mv64360_eth_stop (struct eth_device *dev);
int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
/* return db64360_eth0_poll(); */
int mv64360_eth_open (struct eth_device *dev);
/*************************************************************************
**************************************************************************
**************************************************************************
* The second part is the low level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/********************************************************************************
* Header File for : MV-643xx network interface header
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Gig Bit Ethernet Controller.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
#ifdef CONFIG_MV64360_SRAM_CACHEABLE
/* In case SRAM is cacheable but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case SRAM is cache coherent or non-cacheable */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif
#else
#ifdef CONFIG_NOT_COHERENT_CACHE
/* In case of descriptors on DDR but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case of descriptors on DDR and cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif /* CONFIG_NOT_COHERENT_CACHE */
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
#define CPU_PIPE_FLUSH \
{ \
__asm__ __volatile__ ("eieio"); \
}
/* defines */
/* Default port configuration value */
#define PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
/* Default sdma control value */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_16_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_16_64BIT;
#else
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT;
#endif
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ETTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_1552BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
#define RX_BUFFER_MAX_SIZE 0xFFFF
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
#define RX_BUFFER_MIN_SIZE 0x8
#define TX_BUFFER_MIN_SIZE 0x8
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define RX_DESC_ALIGNED_SIZE 0x20
#define TX_DESC_ALIGNED_SIZE 0x20
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
#define TX_BUF_OFFSET_IN_DESC 0x18
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gap define */
#define ETH_BAR_GAP 0x8
#define ETH_SIZE_REG_GAP 0x8
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII 0
#define ETH_INTERFACE_PCM BIT0
#define ETH_LINK_IS_DOWN 0
#define ETH_LINK_IS_UP BIT1
#define ETH_PORT_AT_HALF_DUPLEX 0
#define ETH_PORT_AT_FULL_DUPLEX BIT2
#define ETH_RX_FLOW_CTRL_DISABLED 0
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
#define ETH_GMII_SPEED_100_10 0
#define ETH_GMII_SPEED_1000 BIT4
#define ETH_MII_SPEED_10 0
#define ETH_MII_SPEED_100 BIT5
#define ETH_NO_TX 0
#define ETH_TX_IN_PROGRESS BIT7
#define ETH_BYPASS_NO_ACTIVE 0
#define ETH_BYPASS_ACTIVE BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
#define ETH_PORT_AT_PARTITION_STATE BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
#define ETH_PORT_TX_FIFO_EMPTY BIT10
/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE 0
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
#define ETH_DEFAULT_RX_QUEUE_0 0
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
#define ETH_RECEIVE_BC_IF_IP 0
#define ETH_REJECT_BC_IF_IP BIT8
#define ETH_RECEIVE_BC_IF_ARP 0
#define ETH_REJECT_BC_IF_ARP BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
#define ETH_PARTITION_DISABLE 0
#define ETH_PARTITION_ENABLE BIT2
/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE BIT0
#define ETH_QUEUE_1_ENABLE BIT1
#define ETH_QUEUE_2_ENABLE BIT2
#define ETH_QUEUE_3_ENABLE BIT3
#define ETH_QUEUE_4_ENABLE BIT4
#define ETH_QUEUE_5_ENABLE BIT5
#define ETH_QUEUE_6_ENABLE BIT6
#define ETH_QUEUE_7_ENABLE BIT7
#define ETH_QUEUE_0_DISABLE BIT8
#define ETH_QUEUE_1_DISABLE BIT9
#define ETH_QUEUE_2_DISABLE BIT10
#define ETH_QUEUE_3_DISABLE BIT11
#define ETH_QUEUE_4_DISABLE BIT12
#define ETH_QUEUE_5_DISABLE BIT13
#define ETH_QUEUE_6_DISABLE BIT14
#define ETH_QUEUE_7_DISABLE BIT15
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB BIT0
#define ETH_RX_BURST_SIZE_1_64BIT 0
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
#define ETH_BLM_RX_NO_SWAP BIT4
#define ETH_BLM_RX_BYTE_SWAP 0
#define ETH_BLM_TX_NO_SWAP BIT5
#define ETH_BLM_TX_BYTE_SWAP 0
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
#define ETH_DESCRIPTORS_NO_SWAP 0
#define ETH_TX_BURST_SIZE_1_64BIT 0
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
/* These macros describes the Port serial control reg (PSCR) bits */
#define ETH_SERIAL_PORT_DISABLE 0
#define ETH_SERIAL_PORT_ENABLE BIT0
#define ETH_FORCE_LINK_PASS BIT1
#define ETH_DO_NOT_FORCE_LINK_PASS 0
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
#define ETH_ADV_NO_FLOW_CTRL 0
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
#define ETH_FORCE_BP_MODE_NO_JAM 0
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
#define ETH_FORCE_LINK_FAIL 0
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
#define ETH_RETRANSMIT_16_ETTEMPTS 0
#define ETH_RETRANSMIT_FOREVER BIT11
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define ETH_DTE_ADV_0 0
#define ETH_DTE_ADV_1 BIT14
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
#define ETH_AUTO_NEG_NO_CHANGE 0
#define ETH_RESTART_AUTO_NEG BIT16
#define ETH_MAX_RX_PACKET_1518BYTE 0
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
#define ETH_SET_EXT_LOOPBACK BIT20
#define ETH_CLR_EXT_LOOPBACK 0
#define ETH_SET_FULL_DUPLEX_MODE BIT21
#define ETH_SET_HALF_DUPLEX_MODE 0
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define ETH_SET_GMII_SPEED_TO_10_100 0
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
#define ETH_SET_MII_SPEED_TO_10 0
#define ETH_SET_MII_SPEED_TO_100 BIT24
/* SMI reg */
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY (BIT0)
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
/* Tx descriptors status */
#define ETH_LC_ERROR (0 )
#define ETH_UR_ERROR (BIT1 )
#define ETH_RL_ERROR (BIT2 )
#define ETH_LLC_SNAP_FORMAT (BIT9 )
/* Rx descriptors status */
#define ETH_CRC_ERROR (0 )
#define ETH_OVERRUN_ERROR (BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
#define ETH_VLAN_TAGGED (BIT19)
#define ETH_BPDU_FRAME (BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
#define ETH_OTHER_FRAME_TYPE (BIT22)
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
#define ETH_FRAME_HEADER_OK (BIT25)
#define ETH_RX_LAST_DESC (BIT26)
#define ETH_RX_FIRST_DESC (BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED (BIT2)
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
#define ETH_FRAME_SET_TO_VLAN (BIT15)
#define ETH_TCP_FRAME (0 )
#define ETH_UDP_FRAME (BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
#define ETH_ZERO_PADDING (BIT19)
#define ETH_TX_LAST_DESC (BIT20)
#define ETH_TX_FIRST_DESC (BIT21)
#define ETH_GEN_CRC (BIT22)
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
#define ETH_AUTO_MODE (BIT30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attributes */
#define EBAR_ATTR_DRAM_CS0 0x00000E00
#define EBAR_ATTR_DRAM_CS1 0x00000D00
#define EBAR_ATTR_DRAM_CS2 0x00000B00
#define EBAR_ATTR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
/* CPU 60x bus or internal SRAM interface */
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
#define EBAR_ATTR_CBS_SRAM 0x00000000
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY BIT0
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
#define EWIN0_ACCESS_MASK 0x0003
#define EWIN1_ACCESS_MASK 0x000C
#define EWIN2_ACCESS_MASK 0x0030
#define EWIN3_ACCESS_MASK 0x00C0
/* typedefs */
typedef enum _eth_port
{
ETH_0 = 0,
ETH_1 = 1,
ETH_2 = 2
}ETH_PORT;
typedef enum _eth_func_ret_status
{
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later. */
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
}ETH_FUNC_RET_STATUS;
typedef enum _eth_queue
{
ETH_Q0 = 0,
ETH_Q1 = 1,
ETH_Q2 = 2,
ETH_Q3 = 3,
ETH_Q4 = 4,
ETH_Q5 = 5,
ETH_Q6 = 6,
ETH_Q7 = 7
} ETH_QUEUE;
typedef enum _addr_win
{
ETH_WIN0,
ETH_WIN1,
ETH_WIN2,
ETH_WIN3,
ETH_WIN4,
ETH_WIN5
} ETH_ADDR_WIN;
typedef enum _eth_target
{
ETH_TARGET_DRAM ,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS ,
ETH_TARGET_PCI0 ,
ETH_TARGET_PCI1
}ETH_TARGET;
typedef struct _eth_rx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short buf_size ; /* Buffer size */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_RX_DESC;
typedef struct _eth_tx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_TX_DESC;
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
typedef struct _pkt_info
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} PKT_INFO;
typedef struct _eth_win_param
{
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
unsigned short attributes; /* BAR attributes. See above macros. */
unsigned int base_addr; /* Window base address in unsigned int form */
unsigned int high_addr; /* Window high address in unsigned int form */
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
bool enable; /* Enable/disable access to the window. */
unsigned short access_ctrl; /* Access ctrl register. see above macros */
} ETH_WIN_PARAM;
/* Ethernet port specific infomation */
typedef struct _eth_port_ctrl
{
ETH_PORT port_num; /* User Ethernet port number */
int port_phy_addr; /* User phy address of Ethrnet port */
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
unsigned int port_config; /* User port configuration value */
unsigned int port_config_extend; /* User port config extend value */
unsigned int port_sdma_config; /* User port SDMA config value */
unsigned int port_serial_control; /* User port serial control value */
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
/* User function to cast virtual address to CPU bus address */
unsigned int (*port_virt_to_phys)(unsigned int addr);
/* User scratch pad for user specific data structures */
void *port_private;
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available Rx resource */
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
/* Returning Rx resource */
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
/* Next available Tx resource */
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
/* Returning Tx resource */
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
/* An extra Tx index to support transmit of multiple buffers per packet */
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
/* Tx/Rx rings size and base variables fields. For driver use */
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
} ETH_PORT_INFO;
/* ethernet.h API list */
/* Port operation control routines */
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
static void eth_port_reset(ETH_PORT eth_port_num);
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
/* Port MAC address routines */
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue);
#if 0 /* FIXME */
static void eth_port_mc_addr (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue,
int option);
#endif
/* PHY and MIB routines */
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int value);
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int* value);
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
int tx_desc_num,
int tx_buff_size,
unsigned int tx_desc_base_addr,
unsigned int tx_buff_base_addr);
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
int rx_desc_num,
int rx_buff_size,
unsigned int rx_desc_base_addr,
unsigned int rx_buff_base_addr);
#endif /* MV64360_ETH_ */

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/* PCI.c - PCI functions */
#include <common.h>
#include <pci.h>
#include "../include/pci.h"
#undef DEBUG
#undef IDE_SET_NATIVE_MODE
static unsigned int local_buses[] = { 0, 0 };
static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
static void gt_pci_bus_mode_display (PCI_HOST host)
{
unsigned int mode;
mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
switch (mode) {
case 0:
printf ("PCI %d bus mode: Conventional PCI\n", host);
break;
case 1:
printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
break;
case 2:
printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
break;
case 3:
printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
break;
default:
printf ("Unknown BUS %d\n", mode);
}
}
#endif
static const unsigned int pci_p2p_configuration_reg[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
static const unsigned int pci_configuration_address[] = {
PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
};
static const unsigned int pci_configuration_data[] = {
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
};
static const unsigned int pci_error_cause_reg[] = {
PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
};
static const unsigned int pci_arbiter_control[] = {
PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
};
static const unsigned int pci_address_space_en[] = {
PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
};
static const unsigned int pci_snoop_control_base_0_low[] = {
PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
};
static const unsigned int pci_snoop_control_top_0[] = {
PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
};
static const unsigned int pci_access_control_base_0_low[] = {
PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
};
static const unsigned int pci_access_control_top_0[] = {
PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
};
static const unsigned int pci_scs_bank_size[2][4] = {
{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
};
static const unsigned int pci_p2p_configuration[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
*
*
* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data)
{
volatile unsigned int DataForAddrReg;
unsigned int functionNum;
unsigned int busNum = 0;
unsigned int addr;
if (pciDevNum > 32) /* illegal device Number */
return;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &addr);
if (addr != DataForAddrReg)
return;
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciReadConfigReg - Read from a PCI0 configuration register
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
* pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum)
{
volatile unsigned int DataForAddrReg;
unsigned int data;
unsigned int functionNum;
unsigned int busNum = 0;
if (pciDevNum > 32) /* illegal device Number */
return 0xffffffff;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &data);
if (data != DataForAddrReg)
return 0xffffffff;
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
*
* Inputs: unsigned int regOffset - The register offset as it apears in the
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
* The configuration Address is configure as type-I (bits[1:0] = '01') due to
* PCI spec referring to P2P.
*
*********************************************************************/
void pciOverBridgeWriteConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum, unsigned int data)
{
unsigned int DataForReg;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
} else {
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT31 | BIT0;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum)
{
unsigned int DataForReg;
unsigned int data;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
} else { /* agent on another bus */
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT0 | BIT31;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciGetRegOffset - Gets the register offset for this region config.
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI register base address
*********************************************************************/
static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
}
}
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
}
static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_0MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_0MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_0MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_0MEMORY3_ADDRESS_REMAP;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_1MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_1MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_1MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_1MEMORY3_ADDRESS_REMAP;
}
}
return PCI_0MEMORY0_ADDRESS_REMAP;
}
/********************************************************************
* pciGetBaseAddress - Gets the base address of a PCI.
* - If the PCI size is 0 then this base address has no meaning!!!
*
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI base address.
*********************************************************************/
unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
{
unsigned int regBase;
unsigned int regEnd;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &regBase);
GT_REG_READ (regOffset + 8, &regEnd);
if (regEnd <= regBase)
return 0xffffffff; /* ERROR !!! */
regBase = regBase << 16;
return regBase;
}
bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
unsigned int bankBase, unsigned int bankLength)
{
unsigned int low = 0xfff;
unsigned int high = 0x0;
unsigned int regOffset = pciGetRegOffset (host, region);
unsigned int remapOffset = pciGetRemapOffset (host, region);
if (bankLength != 0) {
low = (bankBase >> 16) & 0xffff;
high = ((bankBase + bankLength) >> 16) - 1;
}
GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
GT_REG_WRITE (regOffset + 8, high);
if (bankLength != 0) { /* must do AFTER writing maps */
GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
dont support upper 32
in this driver */
}
return true;
}
unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
{
unsigned int low;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
return (low & 0xffff) << 16;
}
unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
{
unsigned int low, high;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
GT_REG_READ (regOffset + 8, &high);
return ((high & 0xffff) + 1) << 16;
}
/* ronen - 7/Dec/03*/
/********************************************************************
* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
* Inputs: one of the PCI BAR
*********************************************************************/
void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
/********************************************************************
* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
*
* Inputs: base and size of PCI SCS
*********************************************************************/
void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
unsigned int pciDramBase, unsigned int pciDramSize)
{
/*ronen different function for 3rd bank. */
unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
pciDramBase = pciDramBase & 0xfffff000;
pciDramBase = pciDramBase | (pciReadConfigReg (host,
PCI_SCS_0_BASE_ADDRESS
+ offset,
SELF) & 0x00000fff);
pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
pciDramBase);
if (pciDramSize == 0)
pciDramSize++;
GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
gtPciEnableInternalBAR (host, bank);
}
/********************************************************************
* pciSetRegionFeatures - This function modifys one of the 8 regions with
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int accessLow;
unsigned int accessHigh;
unsigned int accessTop = baseAddress + regionLength;
if (regionLength == 0) { /* close the region. */
pciDisableAccessRegion (host, region);
return true;
}
/* base Address is store is bits [11:0] */
accessLow = (baseAddress & 0xfff00000) >> 20;
/* All the features are update according to the defines in pci.h (to be on
the safe side we disable bits: [11:0] */
accessLow = accessLow | (features & 0xfffff000);
/* write to the Low Access Region register */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
accessLow);
accessHigh = (accessTop & 0xfff00000) >> 20;
/* write to the High Access Region register */
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
accessHigh - 1);
return true;
}
/********************************************************************
* pciDisableAccessRegion - Disable The given Region by writing MAX size
* to its low Address and MIN size to its high Address.
*
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
*********************************************************************/
void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
{
/* writing back the registers default values. */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
0x01001fff);
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
}
/********************************************************************
* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciArbiterEnable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
return true;
}
/********************************************************************
* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true
*********************************************************************/
bool pciArbiterDisable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
return true;
}
/********************************************************************
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
*
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* Returns: true
*********************************************************************/
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 7) + (externalAgent0 << 8) +
(externalAgent1 << 9) + (externalAgent2 << 10) +
(externalAgent3 << 11) + (externalAgent4 << 12) +
(externalAgent5 << 13);
regData = (regData & 0xffffc07f) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
return true;
}
/********************************************************************
* pciParkingDisable - Park on last option disable, with this function you can
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
*
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 14) + (externalAgent0 << 15) +
(externalAgent1 << 16) + (externalAgent2 << 17) +
(externalAgent3 << 18) + (externalAgent4 << 19) +
(externalAgent5 << 20);
regData = (regData & ~(0x7f << 14)) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
*
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
* grant without asserting frame.
* Returns: Error for illegal broken value otherwise true.
*********************************************************************/
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
{
unsigned int data;
unsigned int regData;
if (brokenValue > 0xf)
return false; /* brokenValue must be 4 bit */
data = brokenValue << 3;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = (regData & 0xffffff87) | data;
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
return true;
}
/********************************************************************
* pciDisableBrokenAgentDetection - This function disable the Broken agent
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciDisableBrokenAgentDetection (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = regData & 0xfffffffd;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciP2PConfig - This function set the PCI_n P2P configurate.
* For more information on the P2P read PCI spec.
*
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
*
* Returns: true.
*********************************************************************/
bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
unsigned int SecondBusHigh,
unsigned int busNum, unsigned int devNum)
{
unsigned int regData;
regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
GT_REG_WRITE (pci_p2p_configuration[host], regData);
return true;
}
/********************************************************************
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
* supports Cache Coherency in the PCI_n interface.
* Inputs: region - One of the four regions.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int snoopXbaseAddress;
unsigned int snoopXtopAddress;
unsigned int data;
unsigned int snoopHigh = baseAddress + regionLength;
if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
return false;
snoopXbaseAddress =
pci_snoop_control_base_0_low[host] + 0x10 * region;
snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
if (regionLength == 0) { /* closing the region */
GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
GT_REG_WRITE (snoopXtopAddress, 0);
return true;
}
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
data = (baseAddress >> 20) | snoopType << 12;
GT_REG_WRITE (snoopXbaseAddress, data);
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
return true;
}
static int gt_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev));
} else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
cfg_addr, offset,
PCI_DEV (dev), bus);
}
return 0;
}
static int gt_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev), value);
} else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset, PCI_DEV (dev), bus,
value);
}
return 0;
}
static void gt_setup_ide (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
u32 bar_response, bar_value;
int bar;
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
0x0);
pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
&bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
bar_value);
}
}
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#if 0
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
unsigned char pin, irq;
pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
if (pin == 1) { /* only allow INT A */
irq = pci_irq_swizzle[(PCI_HOST) hose->
cfg_addr][PCI_DEV (dev)];
if (irq)
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
}
#endif
struct pci_config_table gt_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
{}
};
struct pci_controller pci0_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
struct pci_controller pci1_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
void pci_init_board (void)
{
unsigned int command;
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
local_buses[0] = pci0_hose.first_busno;
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CFG_PCI0_IO_SPACE_PCI,
CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci0_hose.region_count = 2;
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
pciArbiterEnable (PCI_HOST0);
pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST1);
#endif
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;
local_buses[1] = pci1_hose.first_busno;
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CFG_PCI1_IO_SPACE_PCI,
CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci1_hose.region_count = 2;
pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
pci_register_hose (&pci1_hose);
pciArbiterEnable (PCI_HOST1);
pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
}

1984
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board/Marvell/db64360/u-boot.lds Normal file
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

52
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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* main board support/init for the Galileo Eval board DB64460.
*/
#ifndef __64460_H__
#define __64460_H__
/* CPU Configuration bits */
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
#define CPU_CONF_SINGLE_CPU (1 << 11)
#define CPU_CONF_ENDIANESS (1 << 12)
#define CPU_CONF_PIPELINE (1 << 13)
#define CPU_CONF_STOP_RETRY (1 << 17)
#define CPU_CONF_MULTI_DECODE (1 << 18)
#define CPU_CONF_DP_VALID (1 << 19)
#define CPU_CONF_PERR_PROP (1 << 22)
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
#define CPU_CONF_AP_VALID (1 << 26)
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
/* CPU Master Control bits */
#define CPU_MAST_CTL_ARB_EN (1 << 8)
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
#endif /* __64460_H__ */

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#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
SOBJS = ../common/misc.o
OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

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board/Marvell/db64460/config.mk Normal file
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#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# EVB64460 boards
#
TEXT_BASE = 0xfff00000

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board/Marvell/db64460/db64460.c Normal file
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
*/
/*
* db64460.c - main board support/init for the Galileo Eval board.
*/
#include <common.h>
#include <74xx_7xx.h>
#include "../include/memory.h"
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
#include "64460.h"
#include "mv_regs.h"
#undef DEBUG
/*#define DEBUG */
#define MAP_PCI
#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
* board_pre_init wont work right (like in cpu_init_f).
* See also my_remap_gt_regs below. (NTL)
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
/*
* This is a version of the GT register space remapping function that
* doesn't touch globals (meaning, it's ok to run from flash.)
*
* Unfortunately, this has the side effect that a writable
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
*/
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
{
u32 temp;
/* check and see if it's already moved */
/* original ppcboot 1.1.6 source
temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 20)
return;
temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 20);
out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
original ppcboot 1.1.6 source end */
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
}
#ifdef CONFIG_PCI
static void gt_pci_config (void)
{
unsigned int stat;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
* config registers by writing ones to the bus and device.
* We then update the Virtual register with the correct value for the bus and device.
*/
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
}
/* Enable master */
PCI_MASTER_ENABLE (0, SELF);
PCI_MASTER_ENABLE (1, SELF);
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
<<
18);
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
/* ronen - enable only CS0 and Internal reg!! */
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
/*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CFG_GT_REGS);
#endif
}
#endif
/* Setup CPU interface paramaters */
static void gt_cpu_config (void)
{
cpu_t cpu = get_cpu_type ();
ulong tmp;
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64460 P.399 */
#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
tmp |= CPU_CONF_DP_VALID;
tmp |= CPU_CONF_AP_VALID;
tmp |= CPU_CONF_PIPELINE;
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
/* CPU master control register */
tmp = GTREGREAD (CPU_MASTER_CONTROL);
tmp |= CPU_MAST_CTL_ARB_EN;
if ((cpu == CPU_7400) ||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
tmp |= CPU_MAST_CTL_CLEAN_BLK;
tmp |= CPU_MAST_CTL_FLUSH_BLK;
} else {
/* cleanblock must be cleared for CPUs
* that do not support this command (603e, 750)
* see Res#1 */
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
}
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
}
/*
* board_pre_init.
*
* set up gal. device mappings, etc.
*/
int board_pre_init (void)
{
uchar sram_boot = 0;
/*
* set up the GT the way the kernel wants it
* the call to move the GT register space will obviously
* fail if it has already been done, but we're going to assume
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
gt_pci_config ();
#endif
/* mask all external interrupt sources */
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
/* new in MV6446x */
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
/* --------------------- */
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
/* does not exist in MV6446x
GT_REG_WRITE(CPU_INT_0_MASK, 0);
GT_REG_WRITE(CPU_INT_1_MASK, 0);
GT_REG_WRITE(CPU_INT_2_MASK, 0);
GT_REG_WRITE(CPU_INT_3_MASK, 0);
--------------------- */
/* ----- DEVICE BUS SETTINGS ------ */
/*
* EVB
* 0 - SRAM ????
* 1 - RTC ????
* 2 - UART ????
* 3 - Flash checked 32Bit Intel Strata
* boot - BootCS checked 8Bit 29LV040B
*
* Zuma
* 0 - Flash
* boot - BootCS
*/
/*
* the dual 7450 module requires burst access to the boot
* device, so the serial rom copies the boot device to the
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
/* configure device timing */
#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
#endif
#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
#endif
#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
#endif
#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CFG_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
return 0;
}
/* various things to do after relocation */
int misc_init_r ()
{
icache_enable ();
#ifdef CFG_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
mpsc_sdma_init ();
mpsc_init2 ();
#endif
#if 0
/* disable the dcache and MMU */
dcache_lock ();
#endif
return 0;
}
void after_reloc (ulong dest_addr, gd_t * gd)
{
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* right now, assume borad type. (there is just one...after all)
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
/* utility functions */
void debug_led (int led, int mode)
{
volatile int *addr = 0;
int dummy;
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
0x1c000);
break;
}
}
dummy = *addr;
}
int display_mem_map (void)
{
int i, j;
unsigned int base, size, width;
/* SDRAM */
printf ("SD (DDR) RAM\n");
for (i = 0; i <= BANK3; i++) {
base = memoryGetBankBaseAddress (i);
size = memoryGetBankSize (i);
if (size != 0) {
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
i, base, size >> 20);
}
}
/* CPU's PCI windows */
for (i = 0; i <= PCI_HOST1; i++) {
printf ("\nCPU's PCI %d windows\n", i);
base = pciGetSpaceBase (i, PCI_IO);
size = pciGetSpaceSize (i, PCI_IO);
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
size >> 20);
for (j = 0;
j <=
PCI_REGION0
/*ronen currently only first PCI MEM is used 3 */ ;
j++) {
base = pciGetSpaceBase (i, j);
size = pciGetSpaceSize (i, j);
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
}
}
/* Devices */
printf ("\nDEVICES\n");
for (i = 0; i <= DEVICE3; i++) {
base = memoryGetDeviceBaseAddress (i);
size = memoryGetDeviceSize (i);
width = memoryGetDeviceWidth (i) * 8;
printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
if (i == 0)
printf ("\t- EXT SRAM (actual - 1M)\n");
else if (i == 1)
printf ("\t- RTC\n");
else if (i == 2)
printf ("\t- UART\n");
else
printf ("\t- LARGE FLASH\n");
}
/* Bootrom */
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
size = memoryGetDeviceSize (BOOT_DEVICE);
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
base, size >> 20, width);
return (0);
}
/* DRAM check routines copied from gw8260 */
#if defined (CFG_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
/* */
/* DESCRIPTION: */
/* this function performs a double word move from the data at */
/* the source pointer to the location at the destination pointer. */
/* */
/* INPUTS: */
/* unsigned long long *src - pointer to data to move */
/* */
/* OUTPUTS: */
/* unsigned long long *dest - pointer to locate to move data */
/* */
/* RETURNS: */
/* None */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CFG_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaa,
0xcccccccccccccccc,
0xf0f0f0f0f0f0f0f0,
0xff00ff00ff00ff00,
0xffff0000ffff0000,
0xffffffff00000000,
0x00000000ffffffff,
0x0000ffff0000ffff,
0x00ff00ff00ff00ff,
0x0f0f0f0f0f0f0f0f,
0x3333333333333333,
0x5555555555555555
};
/*********************************************************************/
/* NAME: mem_test_data() - test data lines for shorts and opens */
/* */
/* DESCRIPTION: */
/* Tests data lines for shorts and opens by forcing adjacent data */
/* to opposite states. Because the data lines could be routed in */
/* an arbitrary manner the must ensure test patterns ensure that */
/* every case is tested. By using the following series of binary */
/* patterns every combination of adjacent bits is test regardless */
/* of routing. */
/* */
/* ...101010101010101010101010 */
/* ...110011001100110011001100 */
/* ...111100001111000011110000 */
/* ...111111110000000011111111 */
/* */
/* Carrying this out, gives us six hex patterns as follows: */
/* */
/* 0xaaaaaaaaaaaaaaaa */
/* 0xcccccccccccccccc */
/* 0xf0f0f0f0f0f0f0f0 */
/* 0xff00ff00ff00ff00 */
/* 0xffff0000ffff0000 */
/* 0xffffffff00000000 */
/* */
/* The number test patterns will always be given by: */
/* */
/* log(base 2)(number data bits) = log2 (64) = 6 */
/* */
/* To test for short and opens to other signals on our boards. we */
/* simply */
/* test with the 1's complemnt of the paterns as well. */
/* */
/* OUTPUTS: */
/* Displays failing test pattern */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
unsigned long long temp64;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_DATA */
#if defined (CFG_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
/* DESCRIPTION: */
/* This function performs a test to verify that each word im */
/* memory is uniquly addressable. The test sequence is as follows: */
/* */
/* 1) write the address of each word to each word. */
/* 2) verify that each location equals its address */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CFG_MEMTEST_START;
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
for (i = 0; i < size; i++) {
pmem[i] = i;
}
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
#if defined (CFG_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
/* DESCRIPTION: */
/* Marches up through memory. At each location verifies rmask if */
/* read = 1. At each location write wmask if write = 1. Displays */
/* failing address and pattern. */
/* */
/* INPUTS: */
/* volatile unsigned long long * base - start address of test */
/* unsigned int size - number of dwords(64-bit) to test */
/* unsigned long long rmask - read verify mask */
/* unsigned long long wmask - wrtie verify mask */
/* short read - verifies rmask if read = 1 */
/* short write - writes wmask if write = 1 */
/* */
/* OUTPUTS: */
/* Displays failing test pattern and address */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
{
unsigned int i;
unsigned long long temp;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *) &(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
return 1;
}
}
if (write != 0) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *) &(base[i]));
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
/* */
/* DESCRIPTION: */
/* Performs a walking ones through entire physical memory. The */
/* test uses as series of memory marches, mem_march(), to verify */
/* and write the test patterns to memory. The test sequence is as */
/* follows: */
/* 1) march writing 0000...0001 */
/* 2) march verifying 0000...0001 , writing 0000...0010 */
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
/* the write mask equals 1000...0000 */
/* 4) march verifying 1000...0000 */
/* The test fails if any of the memory marches return a failure. */
/* */
/* OUTPUTS: */
/* Displays which pass on the memory test is executing */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CFG_MEMTEST_START;
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
unsigned int i;
mask = 0x01;
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2);
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf ("\b\b\b\b\b\b\b");
}
printf ("Last Pass");
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
/*********************************************************************/
/* NAME: testdram() - calls any enabled memory tests */
/* */
/* DESCRIPTION: */
/* Runs memory tests if the environment test variables are set to */
/* 'y'. */
/* */
/* INPUTS: */
/* testdramdata - If set to 'y', data test is run. */
/* testdramaddress - If set to 'y', address test is run. */
/* testdramwalk - If set to 'y', walking ones test is run */
/* */
/* OUTPUTS: */
/* None */
/* */
/* RETURNS: */
/* 0 - Passed test */
/* 1 - Failed test */
/* */
/* RESTRICTIONS/LIMITATIONS: */
/* */
/* */
/*********************************************************************/
int testdram (void)
{
char *s;
int rundata, runaddress, runwalk;
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("passed\n");
}
return 0;
}
#endif /* CFG_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
/* the kernel data areas. */
/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
if ((temp & 0xffff) == new_loc >> 16)
return;
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
0xffff0000) | (new_loc >> 16);
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
new_loc |
(INTERNAL_SPACE_DECODE)))))
!= temp);
}
void board_prebootm_init ()
{
/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
/* Stop GigE Rx DMA engines */
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
/* Relocate MV64460 internal regs */
my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
invalidate_l1_instruction_cache ();
flush_data_cache ();
dcache_disable ();
}

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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __EVB64460_ETH_H__
#define __EVB64460_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
int db64460_eth0_poll(void);
int db64460_eth0_transmit(unsigned int s, volatile char *p);
void db64460_eth0_disable(void);
bool network_start(bd_t *bis);
#endif /* __EVB64460_ETH_H__ */

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/*
* (C) Copyright 2001
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
*
************************************************************************/
/*
* mpsc.h - header file for MPSC in uart mode (console driver)
*/
#ifndef __MPSC_H__
#define __MPSC_H__
/* include actual Galileo defines */
#include "../include/mv_gen_reg.h"
/* driver related defines */
int mpsc_init(int baud);
void mpsc_sdma_init(void);
void mpsc_init2(void);
int galbrg_set_baudrate(int channel, int rate);
int mpsc_putchar_early(char ch);
char mpsc_getchar_debug(void);
int mpsc_test_char_debug(void);
int mpsc_test_char_sdma(void);
extern int (*mpsc_putchar)(char ch);
extern char (*mpsc_getchar)(void);
extern int (*mpsc_test_char)(void);
#define CHANNEL CONFIG_MPSC_PORT
#define TX_DESC 5
#define RX_DESC 20
#define DESC_FIRST 0x00010000
#define DESC_LAST 0x00020000
#define DESC_OWNER_BIT 0x80000000
#define TX_DEMAND 0x00800000
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)
/* MPSC defines */
#define GALMPSC_CONNECT 0x1
#define GALMPSC_DISCONNECT 0x0
#define GALMPSC_UART 0x1
#define GALMPSC_STOP_BITS_1 0x0
#define GALMPSC_STOP_BITS_2 0x1
#define GALMPSC_CHAR_LENGTH_8 0x3
#define GALMPSC_CHAR_LENGTH_7 0x2
#define GALMPSC_PARITY_ODD 0x0
#define GALMPSC_PARITY_EVEN 0x2
#define GALMPSC_PARITY_MARK 0x3
#define GALMPSC_PARITY_SPACE 0x1
#define GALMPSC_PARITY_NONE -1
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
#define GALMPSC_REG_GAP 0x1000
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
#define GALSDMA_COMMAND_FIRST (1 << 16)
#define GALSDMA_COMMAND_LAST (1 << 17)
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
#define GALSDMA_COMMAND_AUTO (1 << 30)
#define GALSDMA_COMMAND_OWNER (1 << 31)
#define GALSDMA_RX 0
#define GALSDMA_TX 1
/* CHANNEL2 should be CHANNEL1, according to documentation,
* but to work with the current GTREGS file...
*/
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
#define GALSDMA_REG_DIFF 0x2000
/* WRONG in gt64260R.h */
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
#define GALMPSC_0_INT_CAUSE 0xb804
#define GALMPSC_0_INT_MASK 0xb884
#define GALSDMA_MODE_UART 0
#define GALSDMA_MODE_BISYNC 1
#define GALSDMA_MODE_HDLC 2
#define GALSDMA_MODE_TRANSPARENT 3
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
#define GALBRG_REG_GAP 0x0008
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
#endif /* __MPSC_H__ */

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/*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64460X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mv_eth.h - header file for the polled mode GT ethernet driver
*/
#ifndef __DB64460_ETH_H__
#define __DB64460_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <common.h>
#include <net.h>
#include "mv_regs.h"
#include "../common/ppc_error_no.h"
/*************************************************************************
**************************************************************************
**************************************************************************
* The first part is the high level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#endif
/* Port attributes */
/*#define MAX_RX_QUEUE_NUM 8*/
/*#define MAX_TX_QUEUE_NUM 8*/
#define MAX_RX_QUEUE_NUM 1
#define MAX_TX_QUEUE_NUM 1
/* Use one TX queue and one RX queue */
#define MV64460_TX_QUEUE_NUM 1
#define MV64460_RX_QUEUE_NUM 1
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 10 descriptors */
#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
#else
#define MV64460_TX_QUEUE_SIZE 4
#endif
/* Default RX ring size is 4 descriptors */
#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
#else
#define MV64460_RX_QUEUE_SIZE 4
#endif
#ifdef CONFIG_RX_BUFFER_SIZE
#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
#else
#define MV64460_RX_BUFFER_SIZE 1600
#endif
#ifdef CONFIG_TX_BUFFER_SIZE
#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
#else
#define MV64460_TX_BUFFER_SIZE 1600
#endif
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
/* Private data structure used for ethernet device */
struct mv64460_eth_priv {
unsigned int port_num;
struct net_device_stats *stats;
/* to buffer area aligned */
char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
/* Size of Tx Ring per queue */
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
/* Size of Rx Ring per queue */
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
/* Magic Number for Ethernet running */
unsigned int eth_running;
};
int mv64460_eth_init (struct eth_device *dev);
int mv64460_eth_stop (struct eth_device *dev);
int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
/* return db64460_eth0_poll(); */
int mv64460_eth_open (struct eth_device *dev);
/*************************************************************************
**************************************************************************
**************************************************************************
* The second part is the low level driver of the gigE ethernet ports. *
**************************************************************************
**************************************************************************
*************************************************************************/
/********************************************************************************
* Header File for : MV-643xx network interface header
*
* DESCRIPTION:
* This header file contains macros typedefs and function declaration for
* the Marvell Gig Bit Ethernet Controller.
*
* DEPENDENCIES:
* None.
*
*******************************************************************************/
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
#ifdef CONFIG_MV64460_SRAM_CACHEABLE
/* In case SRAM is cacheable but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case SRAM is cache coherent or non-cacheable */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif
#else
#ifdef CONFIG_NOT_COHERENT_CACHE
/* In case of descriptors on DDR but not cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) \
{ \
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
}
#else
/* In case of descriptors on DDR and cache coherent */
#define D_CACHE_FLUSH_LINE(addr, offset) ;
#endif /* CONFIG_NOT_COHERENT_CACHE */
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
#define CPU_PIPE_FLUSH \
{ \
__asm__ __volatile__ ("eieio"); \
}
/* defines */
/* Default port configuration value */
#define PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
ETH_DEFAULT_RX_QUEUE_0 | \
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
ETH_RECEIVE_BC_IF_IP | \
ETH_RECEIVE_BC_IF_ARP | \
ETH_CAPTURE_TCP_FRAMES_DIS | \
ETH_CAPTURE_UDP_FRAMES_DIS | \
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
ETH_DEFAULT_RX_BPDU_QUEUE_0
/* Default port extend configuration value */
#define PORT_CONFIG_EXTEND_VALUE \
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
ETH_PARTITION_DISABLE
/* Default sdma control value */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_16_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_16_64BIT;
#else
#define PORT_SDMA_CONFIG_VALUE \
ETH_RX_BURST_SIZE_4_64BIT | \
GT_ETH_IPG_INT_RX(0) | \
ETH_TX_BURST_SIZE_4_64BIT;
#endif
#define GT_ETH_IPG_INT_RX(value) \
((value & 0x3fff) << 8)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE \
ETH_FORCE_LINK_PASS | \
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
ETH_FORCE_BP_MODE_NO_JAM | \
BIT9 | \
ETH_DO_NOT_FORCE_LINK_FAIL | \
ETH_RETRANSMIT_16_ETTEMPTS | \
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
ETH_DTE_ADV_0 | \
ETH_DISABLE_AUTO_NEG_BYPASS | \
ETH_AUTO_NEG_NO_CHANGE | \
ETH_MAX_RX_PACKET_1552BYTE | \
ETH_CLR_EXT_LOOPBACK | \
ETH_SET_FULL_DUPLEX_MODE | \
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
#define RX_BUFFER_MAX_SIZE 0xFFFF
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
#define RX_BUFFER_MIN_SIZE 0x8
#define TX_BUFFER_MIN_SIZE 0x8
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define RX_DESC_ALIGNED_SIZE 0x20
#define TX_DESC_ALIGNED_SIZE 0x20
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
#define TX_BUF_OFFSET_IN_DESC 0x18
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gap define */
#define ETH_BAR_GAP 0x8
#define ETH_SIZE_REG_GAP 0x8
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII 0
#define ETH_INTERFACE_PCM BIT0
#define ETH_LINK_IS_DOWN 0
#define ETH_LINK_IS_UP BIT1
#define ETH_PORT_AT_HALF_DUPLEX 0
#define ETH_PORT_AT_FULL_DUPLEX BIT2
#define ETH_RX_FLOW_CTRL_DISABLED 0
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
#define ETH_GMII_SPEED_100_10 0
#define ETH_GMII_SPEED_1000 BIT4
#define ETH_MII_SPEED_10 0
#define ETH_MII_SPEED_100 BIT5
#define ETH_NO_TX 0
#define ETH_TX_IN_PROGRESS BIT7
#define ETH_BYPASS_NO_ACTIVE 0
#define ETH_BYPASS_ACTIVE BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
#define ETH_PORT_AT_PARTITION_STATE BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
#define ETH_PORT_TX_FIFO_EMPTY BIT10
/* These macros describes the Port configuration reg (Px_cR) bits */
#define ETH_UNICAST_NORMAL_MODE 0
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
#define ETH_DEFAULT_RX_QUEUE_0 0
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
#define ETH_RECEIVE_BC_IF_IP 0
#define ETH_REJECT_BC_IF_IP BIT8
#define ETH_RECEIVE_BC_IF_ARP 0
#define ETH_REJECT_BC_IF_ARP BIT9
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define ETH_CLASSIFY_EN BIT0
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
#define ETH_PARTITION_DISABLE 0
#define ETH_PARTITION_ENABLE BIT2
/* Tx/Rx queue command reg (RQCR/TQCR)*/
#define ETH_QUEUE_0_ENABLE BIT0
#define ETH_QUEUE_1_ENABLE BIT1
#define ETH_QUEUE_2_ENABLE BIT2
#define ETH_QUEUE_3_ENABLE BIT3
#define ETH_QUEUE_4_ENABLE BIT4
#define ETH_QUEUE_5_ENABLE BIT5
#define ETH_QUEUE_6_ENABLE BIT6
#define ETH_QUEUE_7_ENABLE BIT7
#define ETH_QUEUE_0_DISABLE BIT8
#define ETH_QUEUE_1_DISABLE BIT9
#define ETH_QUEUE_2_DISABLE BIT10
#define ETH_QUEUE_3_DISABLE BIT11
#define ETH_QUEUE_4_DISABLE BIT12
#define ETH_QUEUE_5_DISABLE BIT13
#define ETH_QUEUE_6_DISABLE BIT14
#define ETH_QUEUE_7_DISABLE BIT15
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define ETH_RIFB BIT0
#define ETH_RX_BURST_SIZE_1_64BIT 0
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
#define ETH_BLM_RX_NO_SWAP BIT4
#define ETH_BLM_RX_BYTE_SWAP 0
#define ETH_BLM_TX_NO_SWAP BIT5
#define ETH_BLM_TX_BYTE_SWAP 0
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
#define ETH_DESCRIPTORS_NO_SWAP 0
#define ETH_TX_BURST_SIZE_1_64BIT 0
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
/* These macros describes the Port serial control reg (PSCR) bits */
#define ETH_SERIAL_PORT_DISABLE 0
#define ETH_SERIAL_PORT_ENABLE BIT0
#define ETH_FORCE_LINK_PASS BIT1
#define ETH_DO_NOT_FORCE_LINK_PASS 0
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
#define ETH_ADV_NO_FLOW_CTRL 0
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
#define ETH_FORCE_BP_MODE_NO_JAM 0
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
#define ETH_FORCE_LINK_FAIL 0
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
#define ETH_RETRANSMIT_16_ETTEMPTS 0
#define ETH_RETRANSMIT_FOREVER BIT11
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define ETH_DTE_ADV_0 0
#define ETH_DTE_ADV_1 BIT14
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
#define ETH_AUTO_NEG_NO_CHANGE 0
#define ETH_RESTART_AUTO_NEG BIT16
#define ETH_MAX_RX_PACKET_1518BYTE 0
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
#define ETH_SET_EXT_LOOPBACK BIT20
#define ETH_CLR_EXT_LOOPBACK 0
#define ETH_SET_FULL_DUPLEX_MODE BIT21
#define ETH_SET_HALF_DUPLEX_MODE 0
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define ETH_SET_GMII_SPEED_TO_10_100 0
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
#define ETH_SET_MII_SPEED_TO_10 0
#define ETH_SET_MII_SPEED_TO_100 BIT24
/* SMI reg */
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY (BIT0)
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
/* Tx descriptors status */
#define ETH_LC_ERROR (0 )
#define ETH_UR_ERROR (BIT1 )
#define ETH_RL_ERROR (BIT2 )
#define ETH_LLC_SNAP_FORMAT (BIT9 )
/* Rx descriptors status */
#define ETH_CRC_ERROR (0 )
#define ETH_OVERRUN_ERROR (BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
#define ETH_VLAN_TAGGED (BIT19)
#define ETH_BPDU_FRAME (BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
#define ETH_OTHER_FRAME_TYPE (BIT22)
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
#define ETH_FRAME_HEADER_OK (BIT25)
#define ETH_RX_LAST_DESC (BIT26)
#define ETH_RX_FIRST_DESC (BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED (BIT2)
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
#define ETH_FRAME_SET_TO_VLAN (BIT15)
#define ETH_TCP_FRAME (0 )
#define ETH_UDP_FRAME (BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
#define ETH_ZERO_PADDING (BIT19)
#define ETH_TX_LAST_DESC (BIT20)
#define ETH_TX_FIRST_DESC (BIT21)
#define ETH_GEN_CRC (BIT22)
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
#define ETH_AUTO_MODE (BIT30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attributes */
#define EBAR_ATTR_DRAM_CS0 0x00000E00
#define EBAR_ATTR_DRAM_CS1 0x00000D00
#define EBAR_ATTR_DRAM_CS2 0x00000B00
#define EBAR_ATTR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
/* CPU 60x bus or internal SRAM interface */
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
#define EBAR_ATTR_CBS_SRAM 0x00000000
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY BIT0
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
#define EWIN0_ACCESS_MASK 0x0003
#define EWIN1_ACCESS_MASK 0x000C
#define EWIN2_ACCESS_MASK 0x0030
#define EWIN3_ACCESS_MASK 0x00C0
/* typedefs */
typedef enum _eth_port
{
ETH_0 = 0,
ETH_1 = 1,
ETH_2 = 2
}ETH_PORT;
typedef enum _eth_func_ret_status
{
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later. */
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
}ETH_FUNC_RET_STATUS;
typedef enum _eth_queue
{
ETH_Q0 = 0,
ETH_Q1 = 1,
ETH_Q2 = 2,
ETH_Q3 = 3,
ETH_Q4 = 4,
ETH_Q5 = 5,
ETH_Q6 = 6,
ETH_Q7 = 7
} ETH_QUEUE;
typedef enum _addr_win
{
ETH_WIN0,
ETH_WIN1,
ETH_WIN2,
ETH_WIN3,
ETH_WIN4,
ETH_WIN5
} ETH_ADDR_WIN;
typedef enum _eth_target
{
ETH_TARGET_DRAM ,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS ,
ETH_TARGET_PCI0 ,
ETH_TARGET_PCI1
}ETH_TARGET;
typedef struct _eth_rx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short buf_size ; /* Buffer size */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_RX_DESC;
typedef struct _eth_tx_desc
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int next_desc_ptr; /* Next descriptor pointer */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} ETH_TX_DESC;
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
typedef struct _pkt_info
{
unsigned short byte_cnt ; /* Descriptor buffer byte count */
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts ; /* Descriptor command status */
unsigned int buf_ptr ; /* Descriptor buffer pointer */
unsigned int return_info ; /* User resource return information */
} PKT_INFO;
typedef struct _eth_win_param
{
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
unsigned short attributes; /* BAR attributes. See above macros. */
unsigned int base_addr; /* Window base address in unsigned int form */
unsigned int high_addr; /* Window high address in unsigned int form */
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
bool enable; /* Enable/disable access to the window. */
unsigned short access_ctrl; /* Access ctrl register. see above macros */
} ETH_WIN_PARAM;
/* Ethernet port specific infomation */
typedef struct _eth_port_ctrl
{
ETH_PORT port_num; /* User Ethernet port number */
int port_phy_addr; /* User phy address of Ethrnet port */
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
unsigned int port_config; /* User port configuration value */
unsigned int port_config_extend; /* User port config extend value */
unsigned int port_sdma_config; /* User port SDMA config value */
unsigned int port_serial_control; /* User port serial control value */
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
/* User function to cast virtual address to CPU bus address */
unsigned int (*port_virt_to_phys)(unsigned int addr);
/* User scratch pad for user specific data structures */
void *port_private;
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available Rx resource */
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
/* Returning Rx resource */
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
/* Next available Tx resource */
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
/* Returning Tx resource */
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
/* An extra Tx index to support transmit of multiple buffers per packet */
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
/* Tx/Rx rings size and base variables fields. For driver use */
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
} ETH_PORT_INFO;
/* ethernet.h API list */
/* Port operation control routines */
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
static void eth_port_reset(ETH_PORT eth_port_num);
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
/* Port MAC address routines */
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue);
#if 0 /* FIXME */
static void eth_port_mc_addr (ETH_PORT eth_port_num,
unsigned char *p_addr,
ETH_QUEUE queue,
int option);
#endif
/* PHY and MIB routines */
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int value);
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
unsigned int phy_reg,
unsigned int* value);
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
PKT_INFO *p_pkt_info);
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE tx_queue,
int tx_desc_num,
int tx_buff_size,
unsigned int tx_desc_base_addr,
unsigned int tx_buff_base_addr);
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
ETH_QUEUE rx_queue,
int rx_desc_num,
int rx_buff_size,
unsigned int rx_desc_base_addr,
unsigned int rx_buff_base_addr);
#endif /* MV64460_ETH_ */

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/* PCI.c - PCI functions */
#include <common.h>
#include <pci.h>
#include "../include/pci.h"
#undef DEBUG
#undef IDE_SET_NATIVE_MODE
static unsigned int local_buses[] = { 0, 0 };
static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
static void gt_pci_bus_mode_display (PCI_HOST host)
{
unsigned int mode;
mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
switch (mode) {
case 0:
printf ("PCI %d bus mode: Conventional PCI\n", host);
break;
case 1:
printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
break;
case 2:
printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
break;
case 3:
printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
break;
default:
printf ("Unknown BUS %d\n", mode);
}
}
#endif
static const unsigned int pci_p2p_configuration_reg[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
static const unsigned int pci_configuration_address[] = {
PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
};
static const unsigned int pci_configuration_data[] = {
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
};
static const unsigned int pci_error_cause_reg[] = {
PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
};
static const unsigned int pci_arbiter_control[] = {
PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
};
static const unsigned int pci_address_space_en[] = {
PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
};
static const unsigned int pci_snoop_control_base_0_low[] = {
PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
};
static const unsigned int pci_snoop_control_top_0[] = {
PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
};
static const unsigned int pci_access_control_base_0_low[] = {
PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
};
static const unsigned int pci_access_control_top_0[] = {
PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
};
static const unsigned int pci_scs_bank_size[2][4] = {
{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
};
static const unsigned int pci_p2p_configuration[] = {
PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
};
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
*
*
* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data)
{
volatile unsigned int DataForAddrReg;
unsigned int functionNum;
unsigned int busNum = 0;
unsigned int addr;
if (pciDevNum > 32) /* illegal device Number */
return;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &addr);
if (addr != DataForAddrReg)
return;
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciReadConfigReg - Read from a PCI0 configuration register
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
* pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum)
{
volatile unsigned int DataForAddrReg;
unsigned int data;
unsigned int functionNum;
unsigned int busNum = 0;
if (pciDevNum > 32) /* illegal device Number */
return 0xffffffff;
if (pciDevNum == SELF) { /* configure our configuration space. */
pciDevNum =
(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
0x1f;
busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
0xff0000;
}
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xfc;
DataForAddrReg =
(regOffset | pciDevNum | functionNum | busNum) | BIT31;
GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
GT_REG_READ (pci_configuration_address[host], &data);
if (data != DataForAddrReg)
return 0xffffffff;
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
*
* Inputs: unsigned int regOffset - The register offset as it apears in the
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
* The configuration Address is configure as type-I (bits[1:0] = '01') due to
* PCI spec referring to P2P.
*
*********************************************************************/
void pciOverBridgeWriteConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum, unsigned int data)
{
unsigned int DataForReg;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
} else {
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT31 | BIT0;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum)
{
unsigned int DataForReg;
unsigned int data;
unsigned int functionNum;
functionNum = regOffset & 0x00000700;
pciDevNum = pciDevNum << 11;
regOffset = regOffset & 0xff;
busNum = busNum << 16;
if (pciDevNum == SELF) { /* This board */
DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
} else { /* agent on another bus */
DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
BIT0 | BIT31;
}
GT_REG_WRITE (pci_configuration_address[host], DataForReg);
GT_REG_READ (pci_configuration_data[host], &data);
return data;
}
/********************************************************************
* pciGetRegOffset - Gets the register offset for this region config.
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI register base address
*********************************************************************/
static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_LOW_DECODE_ADDRESS;
case PCI_REGION0:
return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
case PCI_REGION1:
return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
case PCI_REGION2:
return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
case PCI_REGION3:
return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
}
}
return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
}
static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
{
switch (host) {
case PCI_HOST0:
switch (region) {
case PCI_IO:
return PCI_0I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_0MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_0MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_0MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_0MEMORY3_ADDRESS_REMAP;
}
case PCI_HOST1:
switch (region) {
case PCI_IO:
return PCI_1I_O_ADDRESS_REMAP;
case PCI_REGION0:
return PCI_1MEMORY0_ADDRESS_REMAP;
case PCI_REGION1:
return PCI_1MEMORY1_ADDRESS_REMAP;
case PCI_REGION2:
return PCI_1MEMORY2_ADDRESS_REMAP;
case PCI_REGION3:
return PCI_1MEMORY3_ADDRESS_REMAP;
}
}
return PCI_0MEMORY0_ADDRESS_REMAP;
}
/********************************************************************
* pciGetBaseAddress - Gets the base address of a PCI.
* - If the PCI size is 0 then this base address has no meaning!!!
*
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
* OUTPUT: N/A
* RETURNS: PCI base address.
*********************************************************************/
unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
{
unsigned int regBase;
unsigned int regEnd;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &regBase);
GT_REG_READ (regOffset + 8, &regEnd);
if (regEnd <= regBase)
return 0xffffffff; /* ERROR !!! */
regBase = regBase << 16;
return regBase;
}
bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
unsigned int bankBase, unsigned int bankLength)
{
unsigned int low = 0xfff;
unsigned int high = 0x0;
unsigned int regOffset = pciGetRegOffset (host, region);
unsigned int remapOffset = pciGetRemapOffset (host, region);
if (bankLength != 0) {
low = (bankBase >> 16) & 0xffff;
high = ((bankBase + bankLength) >> 16) - 1;
}
GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
GT_REG_WRITE (regOffset + 8, high);
if (bankLength != 0) { /* must do AFTER writing maps */
GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
dont support upper 32
in this driver */
}
return true;
}
unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
{
unsigned int low;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
return (low & 0xffff) << 16;
}
unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
{
unsigned int low, high;
unsigned int regOffset = pciGetRegOffset (host, region);
GT_REG_READ (regOffset, &low);
GT_REG_READ (regOffset + 8, &high);
return ((high & 0xffff) + 1) << 16;
}
/* ronen - 7/Dec/03*/
/********************************************************************
* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
* Inputs: one of the PCI BAR
*********************************************************************/
void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
{
SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
}
/********************************************************************
* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
*
* Inputs: base and size of PCI SCS
*********************************************************************/
void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
unsigned int pciDramBase, unsigned int pciDramSize)
{
/*ronen different function for 3rd bank. */
unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
pciDramBase = pciDramBase & 0xfffff000;
pciDramBase = pciDramBase | (pciReadConfigReg (host,
PCI_SCS_0_BASE_ADDRESS
+ offset,
SELF) & 0x00000fff);
pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
pciDramBase);
if (pciDramSize == 0)
pciDramSize++;
GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
gtPciEnableInternalBAR (host, bank);
}
/********************************************************************
* pciSetRegionFeatures - This function modifys one of the 8 regions with
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int accessLow;
unsigned int accessHigh;
unsigned int accessTop = baseAddress + regionLength;
if (regionLength == 0) { /* close the region. */
pciDisableAccessRegion (host, region);
return true;
}
/* base Address is store is bits [11:0] */
accessLow = (baseAddress & 0xfff00000) >> 20;
/* All the features are update according to the defines in pci.h (to be on
the safe side we disable bits: [11:0] */
accessLow = accessLow | (features & 0xfffff000);
/* write to the Low Access Region register */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
accessLow);
accessHigh = (accessTop & 0xfff00000) >> 20;
/* write to the High Access Region register */
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
accessHigh - 1);
return true;
}
/********************************************************************
* pciDisableAccessRegion - Disable The given Region by writing MAX size
* to its low Address and MIN size to its high Address.
*
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
*********************************************************************/
void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
{
/* writing back the registers default values. */
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
0x01001fff);
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
}
/********************************************************************
* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciArbiterEnable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
return true;
}
/********************************************************************
* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
*
* Inputs: N/A
* Returns: true
*********************************************************************/
bool pciArbiterDisable (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
return true;
}
/********************************************************************
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
*
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* Returns: true
*********************************************************************/
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 7) + (externalAgent0 << 8) +
(externalAgent1 << 9) + (externalAgent2 << 10) +
(externalAgent3 << 11) + (externalAgent4 << 12) +
(externalAgent5 << 13);
regData = (regData & 0xffffc07f) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
return true;
}
/********************************************************************
* pciParkingDisable - Park on last option disable, with this function you can
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
*
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5)
{
unsigned int regData;
unsigned int writeData;
GT_REG_READ (pci_arbiter_control[host], &regData);
writeData = (internalAgent << 14) + (externalAgent0 << 15) +
(externalAgent1 << 16) + (externalAgent2 << 17) +
(externalAgent3 << 18) + (externalAgent4 << 19) +
(externalAgent5 << 20);
regData = (regData & ~(0x7f << 14)) | writeData;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
*
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
* grant without asserting frame.
* Returns: Error for illegal broken value otherwise true.
*********************************************************************/
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
{
unsigned int data;
unsigned int regData;
if (brokenValue > 0xf)
return false; /* brokenValue must be 4 bit */
data = brokenValue << 3;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = (regData & 0xffffff87) | data;
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
return true;
}
/********************************************************************
* pciDisableBrokenAgentDetection - This function disable the Broken agent
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
*
* Inputs: N/A
* Returns: true.
*********************************************************************/
bool pciDisableBrokenAgentDetection (PCI_HOST host)
{
unsigned int regData;
GT_REG_READ (pci_arbiter_control[host], &regData);
regData = regData & 0xfffffffd;
GT_REG_WRITE (pci_arbiter_control[host], regData);
return true;
}
/********************************************************************
* pciP2PConfig - This function set the PCI_n P2P configurate.
* For more information on the P2P read PCI spec.
*
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
*
* Returns: true.
*********************************************************************/
bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
unsigned int SecondBusHigh,
unsigned int busNum, unsigned int devNum)
{
unsigned int regData;
regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
GT_REG_WRITE (pci_p2p_configuration[host], regData);
return true;
}
/********************************************************************
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
* supports Cache Coherency in the PCI_n interface.
* Inputs: region - One of the four regions.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength)
{
unsigned int snoopXbaseAddress;
unsigned int snoopXtopAddress;
unsigned int data;
unsigned int snoopHigh = baseAddress + regionLength;
if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
return false;
snoopXbaseAddress =
pci_snoop_control_base_0_low[host] + 0x10 * region;
snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
if (regionLength == 0) { /* closing the region */
GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
GT_REG_WRITE (snoopXtopAddress, 0);
return true;
}
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
data = (baseAddress >> 20) | snoopType << 12;
GT_REG_WRITE (snoopXbaseAddress, data);
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
return true;
}
static int gt_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev));
} else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
cfg_addr, offset,
PCI_DEV (dev), bus);
}
return 0;
}
static int gt_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
PCI_DEV (dev), value);
} else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
offset, PCI_DEV (dev), bus,
value);
}
return 0;
}
static void gt_setup_ide (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
u32 bar_response, bar_value;
int bar;
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
0x0);
pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
&bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
bar_value);
}
}
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#if 0
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
unsigned char pin, irq;
pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
if (pin == 1) { /* only allow INT A */
irq = pci_irq_swizzle[(PCI_HOST) hose->
cfg_addr][PCI_DEV (dev)];
if (irq)
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
}
#endif
struct pci_config_table gt_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
{}
};
struct pci_controller pci0_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
struct pci_controller pci1_hose = {
/* fixup_irq: gt_fixup_irq, */
config_table:gt_config_table,
};
void pci_init_board (void)
{
unsigned int command;
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
local_buses[0] = pci0_hose.first_busno;
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CFG_PCI0_IO_SPACE_PCI,
CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci0_hose.region_count = 2;
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
pciArbiterEnable (PCI_HOST0);
pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST1);
#endif
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;
local_buses[1] = pci1_hose.first_busno;
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CFG_PCI1_IO_SPACE_PCI,
CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
gt_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
gt_write_config_dword);
pci1_hose.region_count = 2;
pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
pci_register_hose (&pci1_hose);
pciArbiterEnable (PCI_HOST1);
pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MASTER;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
command |= PCI_COMMAND_MEMORY;
pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
}

1985
board/Marvell/db64460/sdram_init.c Normal file
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board/Marvell/db64460/u-boot.lds Normal file
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

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/* Core.h - Basic core logic functions and definitions */
/* Copyright Galileo Technology. */
/*
DESCRIPTION
This header file contains simple read/write macros for addressing
the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
space). The macros take care of Big/Little endian conversions.
*/
#ifndef __INCcoreh
#define __INCcoreh
#include "mv_gen_reg.h"
extern unsigned int INTERNAL_REG_BASE_ADDR;
/****************************************/
/* GENERAL Definitions */
/****************************************/
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _3M 0x00300000
#define _4M 0x00400000
#define _5M 0x00500000
#define _6M 0x00600000
#define _7M 0x00700000
#define _8M 0x00800000
#define _9M 0x00900000
#define _10M 0x00a00000
#define _11M 0x00b00000
#define _12M 0x00c00000
#define _13M 0x00d00000
#define _14M 0x00e00000
#define _15M 0x00f00000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
typedef enum _bool{false,true} bool;
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
#define SHORT_SWAP(X) (X)
#define WORD_SWAP(X) (X)
#define LONG_SWAP(X) ((l64)(X))
#else /* Big Endian */
#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
(((X)&0xff00)<<8)+ \
(((X)&0xff0000)>>8)+ \
(((X)&0xff000000)>>24)
#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
(((X)&0xff00ULL)<<40)+ \
(((X)&0xff0000ULL)<<24)+ \
(((X)&0xff000000ULL)<<8)+ \
(((X)&0xff00000000ULL)>>8)+ \
(((X)&0xff0000000000ULL)>>24)+ \
(((X)&0xff000000000000ULL)>>40)+ \
(((X)&0xff00000000000000ULL)>>56))
#endif
#ifndef NULL
#define NULL 0
#endif
/* Those two definitions were defined to be compatible with MIPS */
#define NONE_CACHEABLE 0x00000000
#define CACHEABLE 0x00000000
/* 750 cache line */
#define CACHE_LINE_SIZE 32
#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
/* Read/Write to/from GT`s internal registers */
#define GT_REG_READ(offset, pData) \
*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
*pData = WORD_SWAP(*pData)
#define GTREGREAD(offset) \
(WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ))
#define GT_REG_WRITE(offset, data) \
*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
WORD_SWAP(data)
/* Write 32/16/8 bit */
#define WRITE_CHAR(address, data) \
*((unsigned char *)(address)) = data
#define WRITE_SHORT(address, data) \
*((unsigned short *)(address)) = data
#define WRITE_WORD(address, data) \
*((unsigned int *)(address)) = data
#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data)
/* Write 32/16/8 bit NonCacheable */
/*
#define GT_WRITE_CHAR(address, data) \
(*((unsigned char *)NONE_CACHEABLE(address))) = data
#define GT_WRITE_SHORT(address, data) \
(*((unsigned short *)NONE_CACHEABLE(address))) = data
#define GT_WRITE_WORD(address, data) \
(*((unsigned int *)NONE_CACHEABLE(address))) = data
*/
/*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
/*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
/*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
/* Read 32/16/8 bits - returns data in variable. */
#define READ_CHAR(address, pData) \
*pData = *((volatile unsigned char *)(address))
#define READ_SHORT(address, pData) \
*pData = *((volatile unsigned short *)(address))
#define READ_WORD(address, pData) \
*pData = *((volatile unsigned int *)(address))
/* Read 32/16/8 bit - returns data direct. */
#define READCHAR(address) \
*((volatile unsigned char *)((address) | NONE_CACHEABLE))
#define READSHORT(address) \
*((volatile unsigned short *)((address) | NONE_CACHEABLE))
#define READWORD(address) \
*((volatile unsigned int *)((address) | NONE_CACHEABLE))
/* Those two Macros were defined to be compatible with MIPS */
#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
/* SET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
#define SET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
regOffset) |= (unsigned int)WORD_SWAP(bits)
/* RESET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'0' in register 0x840 while the other bits stays as is. */
#define RESET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
/* gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
/*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
/*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
/* gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
logic '0' in register 0x840 while the other bits stays as is. */
/*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
#endif /* __INCcoreh */

173
board/Marvell/include/memory.h Normal file
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@ -0,0 +1,173 @@
/* Memory.h - Memory mappings and remapping functions declarations */
/* Copyright - Galileo technology. */
#ifndef __INCmemoryh
#define __INCmemoryh
/* includes */
#include "core.h"
/* defines */
#define DONT_MODIFY 0xffffffff
#define PARITY_SUPPORT 0x40000000
#define MINIMUM_MEM_BANK_SIZE 0x10000
#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
#define MINIMUM_PCI_WINDOW_SIZE 0x10000
#define MINIMUM_ACCESS_WIN_SIZE 0x10000
#define _8BIT 0x00000000
#define _16BIT 0x00100000
#define _32BIT 0x00200000
#define _64BIT 0x00300000
/* typedefs */
typedef struct deviceParam
{ /* boundary values */
unsigned int turnOff; /* 0x0 - 0xf */
unsigned int acc2First; /* 0x0 - 0x1f */
unsigned int acc2Next; /* 0x0 - 0x1f */
unsigned int ale2Wr; /* 0x0 - 0xf */
unsigned int wrLow; /* 0x0 - 0xf */
unsigned int wrHigh; /* 0x0 - 0xf */
unsigned int badrSkew; /* 0x0 - 0x2 */
unsigned int DPEn; /* 0x0 - 0x1 */
unsigned int deviceWidth; /* in Bytes */
} DEVICE_PARAM;
typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
MEM_REGION3,MEM_REGION4,MEM_REGION5, \
MEM_REGION6,MEM_REGION7} \
MEMORY_PROTECT_REGION;*/
/* There are four possible windows that can be defined as protected */
typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
MEM_WINDOW3
} MEMORY_PROTECT_WINDOW;
/* When defining a protected window , this paramter indicates whether it
is accessible or not */
typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
MEMORY_ACCESS;
typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
MEMORY_ACCESS_WRITE;
typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
MEMORY_CACHE_PROTECT;
typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
MEMORY_SNOOP_TYPE;
typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
MEMORY_SNOOP_REGION;
/* There are 21 memory windows dedicated for the varios interfaces (PCI,
devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
address decoding mechanism. */
typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
PCI_0_MEM0_WINDOW = BIT10,
PCI_0_MEM1_WINDOW = BIT11,
PCI_0_MEM2_WINDOW = BIT12,
PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
INTEGRATED_SRAM_WINDOW = BIT19,
INTERNAL_SPACE_WINDOW = BIT20,
ALL_WINDOWS = 0X1FFFFF
} MEMORY_WINDOW;
typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
} MEMORY_WINDOW_STATUS;
typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
#ifdef INCLUDE_PCI_1
,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
#endif /* INCLUDE_PCI_1 */
} PCI_MEM_WINDOW;
/* -------------------------------------------------------------------------------------------------*/
/* functions */
unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
unsigned int memoryGetDeviceBaseAddress(DEVICE device);
/* New at MV6436x */
unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
unsigned int memoryGetBankSize(MEMORY_BANK bank);
unsigned int memoryGetDeviceSize(DEVICE device);
unsigned int memoryGetDeviceWidth(DEVICE device);
/* New at MV6436x */
unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
/* Set a new base and size for one of the memory banks (CS0 - CS3) */
bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
unsigned int bankSize);
bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
/* Change the Internal Register Base Address to a new given Address. */
bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
/* returns internal Register Space Base Address. */
unsigned int memoryGetInternalRegistersSpace(void);
/* Returns the integrated SRAM Base Address. */
unsigned int memoryGetInternalSramBaseAddr(void);
/* -------------------------------------------------------------------------------------------------*/
/* Set new base address for the integrated SRAM. */
void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
/* -------------------------------------------------------------------------------------------------*/
/* Delete a protection feature to a given space. */
void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
/* -------------------------------------------------------------------------------------------------*/
/* Writes a new remap value to the remap register */
unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
unsigned int remapValueHigh,
unsigned int remapValueLow);
/* -------------------------------------------------------------------------------------------------*/
/* Configurate the protection feature to a given space. */
bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
MEMORY_ACCESS gtMemoryAccess,
MEMORY_ACCESS_WRITE gtMemoryWrite,
MEMORY_CACHE_PROTECT cacheProtection,
unsigned int baseAddress,
unsigned int size);
/* Configurate the protection feature to a given space. */
/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
MEMORY_ACCESS memoryAccess,
MEMORY_ACCESS_WRITE memoryWrite,
MEMORY_CACHE_PROTECT cacheProtection,
unsigned int baseAddress,
unsigned int regionLength); */
/* Configurate the snoop feature to a given space. */
bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
MEMORY_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength);
bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
/* Set a new base and size for one of the PCI windows. */
bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
unsigned int pciWindowSize);
/* Disable or enable one of the 21 windows dedicated for the CPU's
address decoding mechanism */
void MemoryDisableWindow(MEMORY_WINDOW window);
void MemoryEnableWindow (MEMORY_WINDOW window);
MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
#endif /* __INCmemoryh */

2288
board/Marvell/include/mv_gen_reg.h Normal file
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293
board/Marvell/include/pci.h Normal file
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@ -0,0 +1,293 @@
/* PCI.h - PCI functions header file */
/* Copyright - Galileo technology. */
#ifndef __INCpcih
#define __INCpcih
/* includes */
#include"core.h"
#include"memory.h"
/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
#define PCI_MAX_DEVICES 22
/* Macros */
/* The next Macros configurate the initiator board (SELF) or any any agent on
the PCI to become: MASTER, response to MEMORY transactions , response to
IO transactions or TWO both MEMORY_IO transactions. Those configuration
are for both PCI0 and PCI1. */
#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
#define MASTER_ENABLE BIT2
#define MEMORY_ENABLE BIT1
#define I_O_ENABLE BIT0
#define SELF 32
/* Agent on the PCI bus may have up to 6 BARS. */
#define BAR0 0x10
#define BAR1 0x14
#define BAR2 0x18
#define BAR3 0x1c
#define BAR4 0x20
#define BAR5 0x24
#define BAR_SEL_MEM_IO BIT0
#define BAR_MEM_TYPE_32_BIT NO_BIT
#define BAR_MEM_TYPE_BELOW_1M BIT1
#define BAR_MEM_TYPE_64_BIT BIT2
#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
#define BAR_PREFETCHABLE BIT3
#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
/* Defines for the access regions. */
#define PREFETCH_ENABLE BIT12
#define PREFETCH_DISABLE NO_BIT
#define DELAYED_READ_ENABLE BIT13
/* #define CACHING_ENABLE BIT14 */
/* aggressive prefetch: PCI slave prefetch two burst in advance*/
#define AGGRESSIVE_PREFETCH BIT16
/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
#define MAX_BURST_4 NO_BIT
#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
#define PCI_ACCESS_PROTECT BIT28
#define PCI_WRITE_PROTECT BIT29
/* typedefs */
typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
REGION6,REGION7} PCI_ACCESS_REGIONS;
typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
PCI_SNOOP_TYPE;
typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
PCI_SNOOP_REGION;
typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
PCI_REGION2,PCI_REGION3,
PCI_IO}
PCI_REGION;
/*ronen 7/Dec/03 */
typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
PCI_LAST_BAR} PCI_INTERNAL_BAR;
typedef struct pciBar {
unsigned int detectBase;
unsigned int base;
unsigned int size;
unsigned int type;
} PCI_BAR;
typedef struct pciDevice {
PCI_HOST host;
char type[40];
unsigned int deviceNum;
unsigned int venID;
unsigned int deviceID;
PCI_BAR bar[6];
} PCI_DEVICE;
typedef struct pciSelfBars {
unsigned int SCS0Base;
unsigned int SCS0Size;
unsigned int SCS1Base;
unsigned int SCS1Size;
unsigned int SCS2Base;
unsigned int SCS2Size;
unsigned int SCS3Base;
unsigned int SCS3Size;
unsigned int internalMemBase;
unsigned int internalIOBase;
unsigned int CS0Base;
unsigned int CS0Size;
unsigned int CS1Base;
unsigned int CS1Size;
unsigned int CS2Base;
unsigned int CS2Size;
unsigned int CS3Base;
unsigned int CS3Size;
unsigned int CSBootBase;
unsigned int CSBootSize;
unsigned int P2PMem0Base;
unsigned int P2PMem0Size;
unsigned int P2PMem1Base;
unsigned int P2PMem1Size;
unsigned int P2PIOBase;
unsigned int P2PIOSize;
unsigned int CPUBase;
unsigned int CPUSize;
} PCI_SELF_BARS;
/* read/write configuration registers on local PCI bus. */
void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data);
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum);
/* read/write configuration registers on another PCI bus. */
void pciOverBridgeWriteConfigReg(PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum,unsigned int data);
unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum);
/* Performs full scane on both PCI and returns all detail possible on the
agents which exist on the bus. */
void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
unsigned int numberOfElment);
/* Master`s memory space */
bool pciMapSpace(PCI_HOST host, PCI_REGION region,
unsigned int remapBase,
unsigned int deviceBase,
unsigned int deviceLength);
unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
/* Slave`s memory space */
void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
#if 0 /* GARBAGE routines - dont use till they get cleaned up */
void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
unsigned int pci0Dev0Length);
void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
unsigned int pci1Dev0Length);
void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
unsigned int pci0Dev1Length);
void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
unsigned int pci1Dev1Length);
void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
unsigned int pci0Dev2Length);
void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
unsigned int pci1Dev2Length);
void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
unsigned int pci0Dev3Length);
void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
unsigned int pci1Dev3Length);
void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
unsigned int pci0DevBootLength);
void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
unsigned int pci1DevBootLength);
void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
unsigned int pci0P2pMem0Length);
void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
unsigned int pci1P2pMem0Length);
void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
unsigned int pci0P2pMem1Length);
void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
unsigned int pci1P2pMem1Length);
void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
unsigned int pci0P2pIoLength);
void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
unsigned int pci1P2pIoLength);
void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
#endif
/* PCI region options */
bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength);
void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
/* PCI arbiter */
bool pciArbiterEnable(PCI_HOST host);
bool pciArbiterDisable(PCI_HOST host);
bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5);
bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
PCI_AGENT_PRIO externalAgent0,
PCI_AGENT_PRIO externalAgent1,
PCI_AGENT_PRIO externalAgent2,
PCI_AGENT_PRIO externalAgent3,
PCI_AGENT_PRIO externalAgent4,
PCI_AGENT_PRIO externalAgent5);
bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5);
bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
/* PCI-to-PCI (P2P) */
bool pciP2PConfig(PCI_HOST host,
unsigned int SecondBusLow,unsigned int SecondBusHigh,
unsigned int busNum,unsigned int devNum);
/* PCI Cache-coherency */
bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength);
PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
#endif /* __INCpcih */

2
board/mpl/pati/cmd_pati.c
View File

@ -296,8 +296,6 @@ static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsig
return 0;
}
/******************************************************************************
* PCI Bridge Registers Dump
*******************************************************************************/

4
board/mpl/pati/plx9056.h
View File

@ -34,9 +34,9 @@
#endif
#define PCI9056_VENDOR_ID PCI_VENDOR_ID
//#define PCI9656_DEVICE_ID PCI_DEVICE_ID
/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */
#define PCI9056_COMMAND PCI_COMMAND
//#define PCI9656_STATUS PCI_STATUS
/*#define PCI9656_STATUS PCI_STATUS */
#define PCI9056_REVISION PCI_REVISION_ID
#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE

24
cpu/74xx_7xx/cpu.c
View File

@ -79,6 +79,10 @@ get_cpu_type(void)
type = CPU_750FX;
break;
case 0x7002:
type = CPU_750GX;
break;
case 0x800C:
type = CPU_7410;
break;
@ -87,6 +91,14 @@ get_cpu_type(void)
type = CPU_7450;
break;
case 0x8001:
type = CPU_7455;
break;
case 0x8002:
type = CPU_7457;
break;
default:
break;
}
@ -124,6 +136,10 @@ int checkcpu (void)
str = "750FX";
break;
case CPU_750GX:
str = "750GX";
break;
case CPU_755:
str = "755";
break;
@ -140,6 +156,14 @@ int checkcpu (void)
str = "MPC7450";
break;
case CPU_7455:
str = "MPC7455";
break;
case CPU_7457:
str = "MPC7457";
break;
default:
printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
return -1;

9
cpu/74xx_7xx/cpu_init.c
View File

@ -39,9 +39,16 @@
void
cpu_init_f (void)
{
if (get_cpu_type() == CPU_7450) {
switch (get_cpu_type()) {
case CPU_7450:
case CPU_7455:
case CPU_7457:
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
break;
default:
/* do nothing */
break;
}
}

58
cpu/74xx_7xx/speed.c
View File

@ -86,13 +86,48 @@ static const int hid1_fx_multipliers_x_10[] = {
int get_clocks (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_750FX
ulong clock = CFG_BUS_CLK * \
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
#else
ulong clock = CFG_BUS_CLK * \
hid1_multipliers_x_10[get_hid1 () >> 28] / 10;
#endif
ulong clock = 0;
/* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) {
case CPU_7455:
case CPU_7457:
/*
* It is assumed that the PLL_EXT line is zero.
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
break;
case CPU_750GX:
case CPU_750FX:
clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break;
case CPU_7450:
case CPU_740:
case CPU_740P:
case CPU_745:
case CPU_750CX:
case CPU_750:
case CPU_750P:
case CPU_755:
case CPU_7400:
case CPU_7410:
/*
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
break;
case CPU_UNKNOWN:
printf ("get_gclk_freq(): unknown CPU type\n");
clock = 0;
return (1);
}
gd->cpu_clk = clock;
gd->bus_clk = CFG_BUS_CLK;
@ -100,12 +135,3 @@ int get_clocks (void)
}
/* ------------------------------------------------------------------------- */
#if 0 /* disabled XXX - use global data instead */
ulong get_bus_freq (ulong gclk_freq)
{
return CFG_BUS_CLK;
}
#endif /* 0 */
/* ------------------------------------------------------------------------- */

7
cpu/74xx_7xx/start.S
View File

@ -42,7 +42,10 @@
#include <asm/cache.h>
#include <asm/mmu.h>
#if !defined(CONFIG_DB64360) && \
!defined(CONFIG_DB64460)
#include <galileo/gt64260R.h>
#endif
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
@ -749,7 +752,9 @@ in_ram:
bne 5b
6:
mr r3, r10 /* Destination Address */
#ifdef CONFIG_AMIGAONEG3SE
#if defined(CONFIG_AMIGAONEG3SE) || \
defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc

4
cpu/mpc5xx/spi.c
View File

@ -354,8 +354,6 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
return (len);
}
/****************************************************************************
* Function: spi_xfer
**************************************************************************** */
@ -412,5 +410,3 @@ ssize_t spi_xfer (size_t count)
}
#endif /* CONFIG_SPI */

2
cpu/mpc5xx/start.S
View File

@ -601,5 +601,3 @@ pll_prog_code_end:
nop
blr
#endif

105
doc/README.db64360 Normal file
View File

@ -0,0 +1,105 @@
This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360.
Author: Ronen Shitrit <rshitrit@il.marvell.com>
This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT.
Supported CPU Types :
+++++++++++++++++++++
IBM750FX (ver 2.3)
MPC7455 (ver 2.1)
Supported CPU Cache Library:
++++++++++++++++++++++++++++
L1 and L2 only.
CPU Control:
++++++++++++
Marvell optimized CPU control settings:
Big Endian
Enable CPU pipeline
Data and address parity checking
AACK# assert after 2 cycles
U-Boot I/O Interface Support:
+++++++++++++++++++++++++++++
- Serial Interface (UART)
This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
- Network Interface
This LSP supports the following network devices:
o MV64360 Gigabit Ethernet Controller device
o Intel 82559 PCI NIC device
- PCI Interface
This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
o Local PCI configuration header control.
o External PCI configuration header control (for other agents on the bus).
o PCI configuration application. Scans and configures the PCI agents on the bus.
o PCI Internal Arbiter activation and configuration.
Memory Interface Support:
+++++++++++++++++++++++++
- DDR
o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
- Devices
o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
o JFFS2
JFFS2 is a crash/power down safe file system for disk-less embedded devices.
This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
Unsupported Features:
+++++++++++++++++++++
Messaging unit - No support for MV64360 Messaging unit.
Watchdog Timer - No support for MV64360 Watchdog unit.
L3 cache - No support for L3 cache on MPC7455
Dual PCU - No support for Dual CPU
PCI-X was never tested
IDMA driver - No support for MV64360 IDMA unit.
BSP Special Considerations:
+++++++++++++++++++++++++++
- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
Test Cases:
###########
UART:
+++++
Check that the UART baud rate is configured to 57600 and 115200, and check:
Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
Load S-Record file over the UART using Windows HyperTerminal.
Network:
++++++++
Use TFTP application to load a debugged executable and execute it.
Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
Memory:
+++++++
Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
o 128MB DIMM consist of 16 x 64Mbit devices
o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
For each chip select device perform data access to verify its accessibility.
Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
Load the U-Boot and:
use the ls command to check correct scan of the JFFS2 on the large flash.
Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
PCI:
++++
1)Insert different PCI cards:
Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
on different slots (0-3) of the PCI and check:
o Correct detection of the PCI devices.
o Correct address mapping of the PCI devices.
2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)

105
doc/README.db64460 Normal file
View File

@ -0,0 +1,105 @@
This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460.
Author: Ronen Shitrit <rshitrit@il.marvell.com>
Supported CPU Types :
+++++++++++++++++++++
IBM750Gx Rev 1.0
MPC7457 Rev 1.1
Supported CPU Cache Library:
++++++++++++++++++++++++++++
L1 and L2 only.
CPU Control:
++++++++++++
Marvell optimized CPU control settings:
Big Endian
Enable CPU pipeline
Data and address parity checking
AACK# assert after 2 cycles
U-Boot I/O Interface Support:
+++++++++++++++++++++++++++++
- Serial Interface (UART)
This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
- Network Interface
This LSP supports the following network devices:
o MV64360 Gigabit Ethernet Controller device
o Intel 82559 PCI NIC device
- PCI Interface
This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
o Local PCI configuration header control.
o External PCI configuration header control (for other agents on the bus).
o PCI configuration application. Scans and configures the PCI agents on the bus.
o PCI Internal Arbiter activation and configuration.
Memory Interface Support:
+++++++++++++++++++++++++
- DDR
o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
- Devices
o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
o JFFS2
JFFS2 is a crash/power down safe file system for disk-less embedded devices.
This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
Unsupported Features:
+++++++++++++++++++++
Messaging unit - No support for MV64360 Messaging unit.
Watchdog Timer - No support for MV64360 Watchdog unit.
L3 cache - No support for L3 cache on MPC7455
Dual PCU - No support for Dual CPU
PCI-X was never tested
IDMA driver - No support for MV64360 IDMA unit.
XOR Engine - No support for MV64460 XOR Engine
BSP Special Considerations:
+++++++++++++++++++++++++++
- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
Test Cases:
###########
UART:
+++++
Check that the UART baud rate is configured to 57600 and 115200, and check:
Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
Load S-Record file over the UART using Windows HyperTerminal.
Network:
++++++++
Use TFTP application to load a debugged executable and execute it.
Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
Memory:
+++++++
Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
o 128MB DIMM consist of 16 x 64Mbit devices
o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
For each chip select device perform data access to verify its accessibility.
Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
Load the U-Boot and:
use the ls command to check correct scan of the JFFS2 on the large flash.
Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
PCI:
++++
1)Insert different PCI cards:
Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
on different slots (0-3) of the PCI and check:
o Correct detection of the PCI devices.
o Correct address mapping of the PCI devices.
2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)

2
drivers/eepro100.c
View File

@ -248,7 +248,7 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet,
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
#if defined(CONFIG_E500)
#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
#define bus_to_phys(a) (a)
#define phys_to_bus(a) (a)
#else

22
examples/Makefile
View File

@ -44,16 +44,16 @@ endif
include $(TOPDIR)/config.mk
SREC = hello_world.srec
BIN = hello_world.bin
BIN = hello_world.bin hello_world
ifeq ($(ARCH),i386)
SREC += 82559_eeprom.srec
BIN += 82559_eeprom.bin
BIN += 82559_eeprom.bin 82559_eeprom
endif
ifeq ($(ARCH),ppc)
SREC += sched.srec
BIN += sched.bin
BIN += sched.bin sched
endif
ifeq ($(ARCH),m68k)
@ -64,18 +64,19 @@ endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
SREC += timer.srec
BIN += timer.bin
BIN += timer.bin timer
endif
# The following example is 8260 specific...
ifeq ($(CPU),mpc8260)
SREC += mem_to_mem_idma2intr.srec
BIN += mem_to_mem_idma2intr.bin
BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
endif
# Utility for resetting i82559 EEPROM
ifeq ($(BOARD),oxc)
SREC += eepro100_eeprom.srec
BIN += eepro100_eeprom.bin eepro100_eeprom
endif
ifeq ($(BIG_ENDIAN),y)
@ -102,14 +103,15 @@ all: .depend $(LIB) $(SREC) $(BIN)
$(LIB): .depend $(LIBOBJS)
$(AR) crv $@ $(LIBOBJS)
%.srec: %.o $(LIB)
%: %.o $(LIB)
$(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
-o $(<:.o=) -e $(<:.o=) $< $(LIB) \
-o $@ -e $(<:.o=) $< $(LIB) \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
%.srec: %
$(OBJCOPY) -O srec $< $@ 2>/dev/null
%.bin: %.srec
$(OBJCOPY) -O binary $(<:.srec=) $@ 2>/dev/null
%.bin: %
$(OBJCOPY) -O binary $< $@ 2>/dev/null
#########################################################################

4
include/74xx_7xx.h
View File

@ -108,10 +108,10 @@ typedef enum __cpu_t {
CPU_740, CPU_750,
CPU_740P, CPU_750P,
CPU_745, CPU_755,
CPU_750CX, CPU_750FX,
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
CPU_7450,
CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;
extern cpu_t get_cpu_type(void);

580
include/configs/DB64360.h Normal file
View File

@ -0,0 +1,580 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
/*************************************************************************
* (c) 2002 Datentechnik AG - Project: Dino
*
*
* $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
*
************************************************************************/
/*************************************************************************
*
* History:
*
* $Log: DB64360.h,v $
* Revision 1.3 2003/04/26 04:58:13 brad
* Cosmetic changes and compiler warning cleanups
*
* Revision 1.2 2003/04/23 15:48:15 ingo
* mem. map output added
*
* Revision 1.1 2003/04/17 09:31:42 ias
* keymile changes 17_04_2003
*
* Revision 1.10 2003/03/06 12:25:04 ias
* 750 FX CPU HID settings updated
*
* Revision 1.9 2003/03/03 16:14:36 ias
* cleanup compiler warnings of printf fuctions
*
* Revision 1.8 2003/03/03 15:11:44 ias
* Marvell MPSC-UART is working
*
* Revision 1.7 2003/02/26 12:15:45 ssu
* adapted default parameters to new board flash address
*
* Revision 1.6 2003/02/25 14:55:42 ssu
* changed default environment parameters
*
* Revision 1.5 2003/02/21 17:14:23 ias
* added extended SPD handling
*
* Revision 1.4 2003/01/14 09:16:08 ias
* PPCBoot for Marvel Beta 0.9
*
* Revision 1.3 2002/12/03 13:56:26 ias
* Environment in flash support added
*
* Revision 1.2 2002/11/29 16:53:29 ias
* Flash support for STM added
*
* Revision 1.1 2002/11/29 13:36:31 ias
* Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
* - working DDRRAM (only 32MByte of 128MB Modul)
* - working I2C Driver for SPD EEPROM read
* - working DUART 16650 for Serial Console
* - working "console"
*
*
*
************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/processor.h>
/* This define must be before the core.h include */
#define CONFIG_DB64360 1 /* this is an DB64360 board */
#ifndef __ASSEMBLY__
#include "../board/Marvell/include/core.h"
#endif
/*-----------------------------------------------------*/
/* #include "../board/db64360/local.h" */
#ifndef __LOCAL_H
#define __LOCAL_H
/* first ethernet */
#define CONFIG_ETHADDR 64:36:00:00:00:01
/* next two ethernet hwaddrs */
#define CONFIG_ETH1ADDR 64:36:00:00:00:02
/* in the atlantis 64360 we have only 2 ETH port on the board,
if we use PCI it has its own MAC addr */
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_H */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_74xx /* we have a 750FX (override local.h) */
#define CONFIG_DB64360 1 /* this is an DB64360 board */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
see sdram_init.c */
#undef CONFIG_ECC /* enable ECC support */
#define CONFIG_MV64360_ECC
/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
#define CONFIG_BOARD_PRE_INIT
#define CFG_BOARD_NAME "DB64360"
#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
/*#define CFG_HUSH_PARSER */
#undef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/*
* The following defines let you select what serial you want to use
* for your console driver.
*
* what to do:
* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
* cable onto the second DUART channel, change the CFG_DUART port from 1
* to 0 below.
*
* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
*/
#define CONFIG_MPSC_PORT 0
/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_NET_MULTI
#define MV_ETH_DEVS 2
/* #undef CONFIG_ETHER_PORT_MII */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
#define CONFIG_BOOTARGS "console=ttyS0,115200"
#endif
/* ronen - the u-boot.bin should be ~0x30000 bytes */
#define CONFIG_EXTRA_ENV_SETTINGS \
"burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
"burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
"bootargs_root=root=/dev/nfs rw\0" \
"bootargs_end=:::DB64360:eth0:none \0"\
"ethprime=mv_enet0\0"\
"standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
/* --------------------------------------------------------------------------------------------------------------- */
/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
#define CONFIG_IPADDR 10.2.40.90
#define CONFIG_SERIAL "No. 1"
#define CONFIG_SERVERIP 10.2.1.126
#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
#define CONFIG_TESTDRAMDATA y
#define CONFIG_TESTDRAMADDRESS n
#define CONFIG_TESETDRAMWALK n
/* --------------------------------------------------------------------------------------------------------------- */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
/* Flash banks JFFS2 should use */
#define CFG_JFFS2_FIRST_BANK 1
#define CFG_JFFS2_NUM_BANKS 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C \
| CFG_CMD_EEPROM \
| CFG_CMD_CACHE \
| CFG_CMD_JFFS2 \
| CFG_CMD_PCI \
| CFG_CMD_NET )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_SPEED 40000 /* I2C speed default */
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
/*
#define CFG_DRAM_TEST
* DRAM tests
* CFG_DRAM_TEST - enables the following tests.
*
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
* addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
*/
#define CFG_DRAM_TEST
#if defined(CFG_DRAM_TEST)
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#define CFG_DRAM_TEST_DATA
#define CFG_DRAM_TEST_ADDRESS
#define CFG_DRAM_TEST_WALK
#endif /* CFG_DRAM_TEST */
#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
#define CFG_BUS_CLK CFG_BUS_HZ
#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
/*ronen - this is the Tclk (MV64360 core) */
#define CFG_TCLK 133000000
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CFG_750FX_HID0 0x8000c084
#define CFG_750FX_HID1 0x54800000
#define CFG_750FX_HID2 0x00000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
/*
* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
* To an unused memory region. The stack will remain in cache until RAM
* is initialized
*/
#define CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
#define CFG_INTERNAL_RAM_ADDR 0xf8000000
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
/* Dummies for BAT 4-7 */
#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
#define CFG_SDRAM2_BASE 0x20000000
#define CFG_SDRAM3_BASE 0x30000000
#define CFG_SDRAM4_BASE 0x40000000
#define CFG_FLASH_BASE 0xfff00000
#define CFG_DFL_BOOTCS_BASE 0xff800000
#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
#define PCI0_IO_BASE_BOOTM 0xfd000000
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS 4
/* What to put in the bats. */
#define CFG_MISC_REGION_BASE 0xf0000000
/* Peripheral Device section */
/*******************************************************/
/* We have on the db64360 Board : */
/* GT-Chipset Register Area */
/* GT-Chipset internal SRAM 256k */
/* SRAM on external device module */
/* Real time clock on external device module */
/* dobble UART on external device module */
/* Data flash on external device module */
/* Boot flash on external device module */
/*******************************************************/
#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
/* c 4 a 8 2 4 1 c */
/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
/* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
/* ronen - update MPP Control MV64360*/
#define CFG_MPP_CONTROL_0 0x02222222
#define CFG_MPP_CONTROL_1 0x11333011
#define CFG_MPP_CONTROL_2 0x40431111
#define CFG_MPP_CONTROL_3 0x00000044
/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
/* gpp[31] gpp[30] gpp[29] gpp[28] */
/* gpp[27] gpp[24]*/
/* gpp[19:14] */
/* setup new config_value for MV64360 DDR-RAM !! */
# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
#define CFG_DUART_IO CFG_DEV2_SPACE
#define CFG_DUART_CHAN 1 /* channel to use for console */
#define CFG_INIT_CHAN1
#define CFG_INIT_CHAN2
#define SRAM_BASE CFG_DEV0_SPACE
#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
/* PCI MEMORY MAP section */
#define CFG_PCI0_MEM_BASE 0x80000000
#define CFG_PCI0_MEM_SIZE _128M
#define CFG_PCI1_MEM_BASE 0x88000000
#define CFG_PCI1_MEM_SIZE _128M
#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
/* PCI I/O MAP section */
#define CFG_PCI0_IO_BASE 0xfa000000
#define CFG_PCI0_IO_SIZE _16M
#define CFG_PCI1_IO_BASE 0xfb000000
#define CFG_PCI1_IO_SIZE _16M
#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
#if defined (CONFIG_750CX)
#define CFG_PCI_IDSEL 0x0
#else
#define CFG_PCI_IDSEL 0x30
#endif
/*----------------------------------------------------------------------
* Initial BAT mappings
*/
/* NOTES:
* 1) GUARDED and WRITE_THRU not allowed in IBATS
* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
*/
/* SDRAM */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT0U CFG_IBAT0U
/* init ram */
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
/* PCI0, PCI1 in one BAT */
#define CFG_IBAT2L BATL_NO_ACCESS
#define CFG_IBAT2U CFG_DBAT2U
#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* GT regs, bootrom, all the devices, PCI I/O */
#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U CFG_IBAT3U
/* I2C addresses for the two DIMM SPD chips */
#define DIMM0_I2C_ADDR 0x56
#define DIMM1_I2C_ADDR 0x54
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
#define CFG_FLASH_CFI 1
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* L2CR setup -- make sure this is right for your board!
* look in include/mpc74xx.h for the defines used here
*/
#define CFG_L2
#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
#define L2_INIT 0
#else
#define L2_INIT 0
/*
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
*/
#endif
#define L2_ENABLE (L2_INIT | L2CR_L2E)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_BOARD_ASM_INIT 1
#endif /* __CONFIG_H */

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include/configs/DB64460.h Normal file
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/processor.h>
/* This define must be before the core.h include */
#define CONFIG_DB64460 1 /* this is an DB64460 board */
#ifndef __ASSEMBLY__
#include "../board/Marvell/include/core.h"
#endif
/*-----------------------------------------------------*/
/* #include "../board/db64460/local.h" */
#ifndef __LOCAL_H
#define __LOCAL_H
#define CONFIG_ETHADDR 64:46:00:00:00:01
#define CONFIG_ETH1ADDR 64:46:00:00:00:02
#define CONFIG_ETH2ADDR 64:46:00:00:00:03
#define CONFIG_ENV_OVERWRITE
#endif /* __CONFIG_H */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_74xx /* we have a 750FX (override local.h) */
#define CONFIG_DB64460 1 /* this is an DB64460 board */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
see sdram_init.c */
#undef CONFIG_ECC /* enable ECC support */
#define CONFIG_MV64460_ECC
/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
#define CONFIG_BOARD_PRE_INIT
#define CFG_BOARD_NAME "DB64460"
#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
/*#define CFG_HUSH_PARSER */
#undef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/*
* The following defines let you select what serial you want to use
* for your console driver.
*
* what to do:
* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
* cable onto the second DUART channel, change the CFG_DUART port from 1
* to 0 below.
*
* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
*/
#define CONFIG_MPSC_PORT 0
/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_NET_MULTI
#define MV_ETH_DEVS 3
/* #undef CONFIG_ETHER_PORT_MII */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
/* ronen - autoboot using tftp */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
#define CONFIG_BOOTARGS "console=ttyS0,115200"
#endif
/* ronen - the u-boot.bin should be ~0x30000 bytes */
#define CONFIG_EXTRA_ENV_SETTINGS \
"burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
"burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
"bootargs_root=root=/dev/nfs rw\0" \
"bootargs_end=:::DB64460:eth0:none \0"\
"ethprime=mv_enet0\0"\
"standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
/* --------------------------------------------------------------------------------------------------------------- */
/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
#define CONFIG_IPADDR 10.2.40.90
#define CONFIG_SERIAL "No. 1"
#define CONFIG_SERVERIP 10.2.1.126
#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
#define CONFIG_TESTDRAMDATA y
#define CONFIG_TESTDRAMADDRESS n
#define CONFIG_TESETDRAMWALK n
/* --------------------------------------------------------------------------------------------------------------- */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
/* Flash banks JFFS2 should use */
#define CFG_JFFS2_FIRST_BANK 1
#define CFG_JFFS2_NUM_BANKS 1
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C \
| CFG_CMD_EEPROM \
| CFG_CMD_CACHE \
| CFG_CMD_JFFS2 \
| CFG_CMD_PCI \
| CFG_CMD_NET )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_SPEED 40000 /* I2C speed default */
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
/*
#define CFG_DRAM_TEST
* DRAM tests
* CFG_DRAM_TEST - enables the following tests.
*
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
* addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
*/
#define CFG_DRAM_TEST
#if defined(CFG_DRAM_TEST)
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#define CFG_DRAM_TEST_DATA
#define CFG_DRAM_TEST_ADDRESS
#define CFG_DRAM_TEST_WALK
#endif /* CFG_DRAM_TEST */
#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
#define CFG_BUS_CLK CFG_BUS_HZ
#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
/*ronen - this is the Tclk (MV64460 core) */
#define CFG_TCLK 133000000
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CFG_750FX_HID0 0x8000c084
#define CFG_750FX_HID1 0x54800000
#define CFG_750FX_HID2 0x00000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
*/
/*
* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
* To an unused memory region. The stack will remain in cache until RAM
* is initialized
*/
#define CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
#define CFG_INTERNAL_RAM_ADDR 0xf8000000
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
/* Dummies for BAT 4-7 */
#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
#define CFG_SDRAM2_BASE 0x20000000
#define CFG_SDRAM3_BASE 0x30000000
#define CFG_SDRAM4_BASE 0x40000000
#define CFG_FLASH_BASE 0xfff00000
#define CFG_DFL_BOOTCS_BASE 0xff800000
#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
#define PCI0_IO_BASE_BOOTM 0xfd000000
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS 4
/* What to put in the bats. */
#define CFG_MISC_REGION_BASE 0xf0000000
/* Peripheral Device section */
/*******************************************************/
/* We have on the db64460 Board : */
/* GT-Chipset Register Area */
/* GT-Chipset internal SRAM 256k */
/* SRAM on external device module */
/* Real time clock on external device module */
/* dobble UART on external device module */
/* Data flash on external device module */
/* Boot flash on external device module */
/*******************************************************/
#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
/* c 4 a 8 2 4 1 c */
/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
/* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
/* ronen - update MPP Control MV64460*/
#define CFG_MPP_CONTROL_0 0x02222222
#define CFG_MPP_CONTROL_1 0x11333011
#define CFG_MPP_CONTROL_2 0x40431111
#define CFG_MPP_CONTROL_3 0x00000044
/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
/* gpp[31] gpp[30] gpp[29] gpp[28] */
/* gpp[27] gpp[24]*/
/* gpp[19:14] */
/* setup new config_value for MV64460 DDR-RAM !! */
# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
#define CFG_DUART_IO CFG_DEV2_SPACE
#define CFG_DUART_CHAN 1 /* channel to use for console */
#define CFG_INIT_CHAN1
#define CFG_INIT_CHAN2
#define SRAM_BASE CFG_DEV0_SPACE
#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
/* PCI MEMORY MAP section */
#define CFG_PCI0_MEM_BASE 0x80000000
#define CFG_PCI0_MEM_SIZE _128M
#define CFG_PCI1_MEM_BASE 0x88000000
#define CFG_PCI1_MEM_SIZE _128M
#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
/* PCI I/O MAP section */
#define CFG_PCI0_IO_BASE 0xfa000000
#define CFG_PCI0_IO_SIZE _16M
#define CFG_PCI1_IO_BASE 0xfb000000
#define CFG_PCI1_IO_SIZE _16M
#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
#if defined (CONFIG_750CX)
#define CFG_PCI_IDSEL 0x0
#else
#define CFG_PCI_IDSEL 0x30
#endif
/*----------------------------------------------------------------------
* Initial BAT mappings
*/
/* NOTES:
* 1) GUARDED and WRITE_THRU not allowed in IBATS
* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
*/
/* SDRAM */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT0U CFG_IBAT0U
/* init ram */
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
/* PCI0, PCI1 in one BAT */
#define CFG_IBAT2L BATL_NO_ACCESS
#define CFG_IBAT2U CFG_DBAT2U
#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* GT regs, bootrom, all the devices, PCI I/O */
#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U CFG_IBAT3U
/* I2C addresses for the two DIMM SPD chips */
#define DIMM0_I2C_ADDR 0x56
#define DIMM1_I2C_ADDR 0x54
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
#define CFG_FLASH_CFI 1
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* L2CR setup -- make sure this is right for your board!
* look in include/mpc74xx.h for the defines used here
*/
#define CFG_L2
#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
#define L2_INIT 0
#else
#define L2_INIT 0
/*
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
*/
#endif
#define L2_ENABLE (L2_INIT | L2CR_L2E)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_BOARD_ASM_INIT 1
#endif /* __CONFIG_H */

5
include/configs/PATI.h
View File

@ -129,8 +129,6 @@
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
/*
@ -185,9 +183,6 @@
SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control
*-----------------------------------------------------------------------

26
net/eth.c
View File

@ -31,23 +31,25 @@
extern int gt6426x_eth_initialize(bd_t *bis);
#endif
extern int au1x00_enet_initialize(bd_t*);
extern int dc21x4x_initialize(bd_t*);
extern int e1000_initialize(bd_t*);
extern int eepro100_initialize(bd_t*);
extern int eth_3com_initialize(bd_t*);
extern int fec_initialize(bd_t*);
extern int inca_switch_initialize(bd_t*);
extern int mpc5xxx_fec_initialize(bd_t*);
extern int mv6436x_eth_initialize(bd_t *);
extern int mv6446x_eth_initialize(bd_t *);
extern int natsemi_initialize(bd_t*);
extern int ns8382x_initialize(bd_t*);
extern int dc21x4x_initialize(bd_t*);
extern int eth_3com_initialize(bd_t*);
extern int pcnet_initialize(bd_t*);
extern int fec_initialize(bd_t*);
extern int scc_initialize(bd_t*);
extern int inca_switch_initialize(bd_t*);
extern int ppc_4xx_eth_initialize(bd_t *);
extern int plb2800_eth_initialize(bd_t*);
extern int mpc5xxx_fec_initialize(bd_t*);
extern int ppc_4xx_eth_initialize(bd_t *);
extern int rtl8139_initialize(bd_t*);
extern int scc_initialize(bd_t*);
extern int skge_initialize(bd_t*);
extern int tsec_initialize(bd_t*);
extern int au1x00_enet_initialize(bd_t*);
extern int rtl8139_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
@ -104,6 +106,12 @@ int eth_initialize(bd_t *bis)
eth_devices = NULL;
eth_current = NULL;
#ifdef CONFIG_DB64360
mv6436x_eth_initialize(bis);
#endif
#ifdef CONFIG_DB64460
mv6446x_eth_initialize(bis);
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
ppc_4xx_eth_initialize(bis);
#endif