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arm: mx5: Add M53Menlo board

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Add Menlosystems M53 board, based on the M53 SoM.
This board has Ethernet, USB host, USB gadget, UART and LCD on it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2018-10-04 21:24:14 +02:00 committed by Stefano Babic
parent ed85f77190
commit 39cb4f3c25
8 changed files with 947 additions and 0 deletions
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6
arch/arm/mach-imx/mx5/Kconfig
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@ -30,6 +30,11 @@ config TARGET_KP_IMX53
select MX53
imply CMD_DM
config TARGET_M53MENLO
bool "Support m53menlo"
select MX53
select SUPPORT_SPL
config TARGET_MX51EVK
bool "Support mx51evk"
select BOARD_LATE_INIT
@ -89,6 +94,7 @@ source "board/freescale/mx53smd/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/k+p/kp_imx53/Kconfig"
source "board/menlo/m53menlo/Kconfig"
source "board/technologic/ts4800/Kconfig"
endif

15
board/menlo/m53menlo/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_M53MENLO
config SYS_BOARD
default "m53menlo"
config SYS_VENDOR
default "menlo"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "m53menlo"
endif

7
board/menlo/m53menlo/MAINTAINERS Normal file
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@ -0,0 +1,7 @@
M53MENLO BOARD
M: Marek Vasut <marex@denx.de>
M: Olaf Mandel <o.mandel@menlosystems.com>
S: Maintained
F: board/menlo/m53menlo/
F: include/configs/m53menlo.h
F: configs/m53menlo_defconfig

9
board/menlo/m53menlo/Makefile Normal file
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@ -0,0 +1,9 @@
#
# Menlosystems M53Menlo
# Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
# Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := m53menlo.o

91
board/menlo/m53menlo/imximage.cfg Normal file
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@ -0,0 +1,91 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* M53 DRAM init values
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
/* Boot Offset 0x400, valid for both SD and NAND boot. */
BOOT_OFFSET FLASH_OFFSET_STANDARD
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
/* ESDCTL */
DATA 4 0x63fd9088 0x32383535
DATA 4 0x63fd9090 0x40383538
DATA 4 0x63fd907c 0x0136014d
DATA 4 0x63fd9080 0x01510141
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x555952e3
DATA 4 0x63fd9010 0xb68e8b63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x092080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x09208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00001800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901c 0x00000000

513
board/menlo/m53menlo/m53menlo.c Normal file
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@ -0,0 +1,513 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Menlosystems M53Menlo board
*
* Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
* Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
#include <asm/spl.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <splash.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
static u32 mx53_dram_size[2];
ulong board_get_usable_ram_top(ulong total_size)
{
/*
* WARNING: We must override get_effective_memsize() function here
* to report only the size of the first DRAM bank. This is to make
* U-Boot relocator place U-Boot into valid memory, that is, at the
* end of the first DRAM bank. If we did not override this function
* like so, U-Boot would be placed at the address of the first DRAM
* bank + total DRAM size - sizeof(uboot), which in the setup where
* each DRAM bank contains 512MiB of DRAM would result in placing
* U-Boot into invalid memory area close to the end of the first
* DRAM bank.
*/
return PHYS_SDRAM_2 + mx53_dram_size[1];
}
int dram_init(void)
{
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
return 0;
}
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
if (port == 0) {
/* USB OTG PWRON */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
PAD_CTL_PKE |
PAD_CTL_DSE_HIGH));
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
/* USB OTG Over Current */
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
} else if (port == 1) {
/* USB Host PWRON */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
PAD_CTL_PKE |
PAD_CTL_DSE_HIGH));
gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
/* USB Host Over Current */
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
}
return 0;
}
#endif
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
/* MDIO pads */
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
/* FEC 0 pads */
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
/* FEC 1 pads */
NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg = {
MMC_SDHC1_BASE_ADDR,
};
int board_mmc_getcd(struct mmc *mmc)
{
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_input(IMX_GPIO_NR(1, 1));
return !gpio_get_value(IMX_GPIO_NR(1, 1));
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
};
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
#endif
#ifdef CONFIG_VIDEO
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
int ret;
/* For ETM0430G0DH6 model, this must be enabled before the clock. */
gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
/*
* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
*/
ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
if (ret)
puts("IPU: Failed to configure LDB clock\n");
/* Configure CCM_CSCMR2 */
clrsetbits_le32(&mxc_ccm->cscmr2,
(0x7 << 26) | BIT(10) | BIT(8),
(0x5 << 26) | BIT(10) | BIT(8));
/* Configure LDB_CTRL */
writel(0x201, 0x53fa8008);
}
static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
{
/* For ETM0430G0DH6 model, this must be enabled before the clock. */
gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
/*
* Set LVDS clock to 9 MHz for the display. The PLL4 is set to
* 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
*/
enable_lvds_clock(dev, 63);
}
static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
{
/*
* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
*/
enable_lvds_clock(dev, 233);
/* For ETM0700G0DH6 model, this may be enabled after the clock. */
gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
}
static const char *lvds_compat_string;
static int detect_lvds(struct display_info_t const *dev)
{
u8 touchid[23];
u8 *touchptr = &touchid[0];
int ret;
ret = i2c_set_bus_num(0);
if (ret)
return 0;
/* Touchscreen is at address 0x38, ID register is 0xbb. */
ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
if (ret)
return 0;
/* EP0430 prefixes the response with 0xbb, skip it. */
if (*touchptr == 0xbb)
touchptr++;
/* Skip the 'EP' prefix. */
touchptr += 2;
ret = !memcmp(touchptr, &dev->mode.name[7], 4);
if (ret)
lvds_compat_string = dev->mode.name;
return ret;
}
void board_preboot_os(void)
{
/* Power off the LCD to prevent awful color flicker */
gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
}
int ft_board_setup(void *blob, bd_t *bd)
{
if (lvds_compat_string)
do_fixup_by_path_string(blob, "/panel", "compatible",
lvds_compat_string);
return 0;
}
struct display_info_t const displays[] = {
{
.bus = 0,
.addr = 0,
.detect = detect_lvds,
.enable = enable_lvds_etm0430g0dh6,
.pixfmt = IPU_PIX_FMT_RGB666,
.mode = {
.name = "edt,etm0430g0dh6",
.refresh = 60,
.xres = 480,
.yres = 272,
.pixclock = 111111, /* picosecond (9 MHz) */
.left_margin = 2,
.right_margin = 2,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 41,
.vsync_len = 10,
.sync = 0x40000000,
.vmode = FB_VMODE_NONINTERLACED
}
}, {
.bus = 0,
.addr = 0,
.detect = detect_lvds,
.enable = enable_lvds_etm0700g0dh6,
.pixfmt = IPU_PIX_FMT_RGB666,
.mode = {
.name = "edt,etm0700g0dh6",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 30048, /* picosecond (33.28 MHz) */
.left_margin = 40,
.right_margin = 88,
.upper_margin = 10,
.lower_margin = 33,
.hsync_len = 128,
.vsync_len = 2,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
}
};
size_t display_count = ARRAY_SIZE(displays);
#endif
#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location default_splash_locations[] = {
{
.name = "mmc_fs",
.storage = SPLASH_STORAGE_MMC,
.flags = SPLASH_STORAGE_FS,
.devpart = "0:1",
},
};
int splash_screen_prepare(void)
{
return splash_source_load(default_splash_locations,
ARRAY_SIZE(default_splash_locations));
}
#endif
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c_pads[] = {
/* I2C1 */
NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
/* I2C2 */
NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
static void setup_iomux_video(void)
{
static const iomux_v3_cfg_t lcd_pads[] = {
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
};
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}
static void setup_iomux_nand(void)
{
static const iomux_v3_cfg_t nand_pads[] = {
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
};
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
static void m53_set_clock(void)
{
int ret;
const u32 ref_clk = MXC_HCLK;
const u32 dramclk = 400;
u32 cpuclk;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
gpio_direction_input(IMX_GPIO_NR(4, 0));
/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
if (ret)
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
if (ret) {
printf("CPU: Switch peripheral clock to %dMHz failed\n",
dramclk);
}
ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
if (ret)
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
}
static void m53_set_nand(void)
{
u32 i;
/* NAND flash is muxed on ATA pins */
setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
for (i = 0x4; i < 0x94; i += 0x18) {
clrbits_le32(WEIM_BASE_ADDR + i,
WEIM_GCR2_MUX16_BYP_GRANT_MASK);
}
mxc_set_clock(0, 33, MXC_NFC_CLK);
enable_nfc_clk(1);
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
setup_iomux_i2c();
setup_iomux_nand();
setup_iomux_video();
m53_set_clock();
mxc_set_sata_internal_clock();
/* NAND clock @ 33MHz */
m53_set_nand();
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int checkboard(void)
{
puts("Board: Menlosystems M53Menlo\n");
return 0;
}
/*
* NAND SPL
*/
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
setup_iomux_nand();
m53_set_clock();
m53_set_nand();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NAND;
}
#endif

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configs/m53menlo_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x71000000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_M53MENLO=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FUSE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Menlosystems M53Menlo configuration
* Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
* Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
*/
#ifndef __M53MENLO_CONFIG_H__
#define __M53MENLO_CONFIG_H__
#include <asm/arch/imx-regs.h>
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Memory configurations
*/
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START 0x70000000
#define CONFIG_SYS_MEMTEST_END 0x8ff00000
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
/*
* Serial Driver
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#endif
/*
* NAND
*/
#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* Environment is in NAND */
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#endif
/*
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC0"
#endif
/*
* I2C
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
#endif
/*
* RTC
*/
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#endif
/*
* SATA
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
#define CONFIG_LBA48
#endif
/*
* LCD
*/
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
#endif
/* LVDS display */
#define CONFIG_SYS_LDB_CLOCK 33260000
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_SPLASH_SOURCE
/* IIM Fuses */
#define CONFIG_FSL_IIM
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTFILE "boot/fitImage"
#define CONFIG_LOADADDR 0x70800000
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
* NAND SPL
*/
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
#define CONFIG_SPL_TEXT_BASE 0x70008000
#define CONFIG_SPL_PAD_TO 0x8000
#define CONFIG_SPL_STACK 0x70004000
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/*
* Extra Environments
*/
#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_HOSTNAME "m53menlo"
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttymxc0\0" \
"baudrate=115200\0" \
"bootscript=boot.scr\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"rootpath=/srv/\0" \
"kernel_addr_r=0x72000000\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"netdev=eth0\0" \
"splashsource=mmc_fs\0" \
"splashfile=usplash.bmp.gz\0" \
"splashimage=0x88000000\0" \
"splashpos=m,m\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
"addip=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off\0" \
"addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
"addmisc=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
"mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
"${kernel_addr_r} ${bootfile}\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
"mmc_mmc=" \
"run mmcload mmcargs addargs ; " \
"bootm ${kernel_addr_r}\0" \
"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"net_nfs=" \
"run netload nfsargs addip addargs ; " \
"bootm ${kernel_addr_r}\0" \
"nfsargs=" \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
"try_bootscript=" \
"mmc rescan;" \
"if test -e mmc 0:1 ${bootscript} ; then " \
"if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
"then ; " \
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
"fi\0"
#endif /* __M53MENLO_CONFIG_H__ */