i2c: Remove non-DM code from ihs_i2c.c
This driver and it's only user are converted to DM_I2C, remove legacy code. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
14376b8e6c
commit
38a671d21e
24
README
24
README
@ -1527,30 +1527,6 @@ The following options need to be configured:
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9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
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with a fix speed from 100000 and the slave addr 0!
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- drivers/i2c/ihs_i2c.c
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- activate this driver with CONFIG_SYS_I2C_IHS
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- CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
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- CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
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- CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
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- CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
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- CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
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- CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
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- CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
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- CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
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- CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
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- CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
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- CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
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- CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
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- activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
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- CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
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- CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
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- CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
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- CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
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- CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
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- CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
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- CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
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- CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -6,19 +6,14 @@
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#include <common.h>
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#include <i2c.h>
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#if CONFIG_IS_ENABLED(DM_I2C)
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#include <dm.h>
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#include <regmap.h>
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#else
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#include <gdsys_fpga.h>
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#endif
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/unaligned.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct ihs_i2c_priv {
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uint speed;
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struct regmap *map;
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@ -39,37 +34,6 @@ struct ihs_i2c_regs {
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#define ihs_i2c_get(map, member, valp) \
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regmap_get(map, struct ihs_i2c_regs, member, valp)
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#else /* !CONFIG_DM_I2C */
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_SET_REG(fld, val) \
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do { \
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if (I2C_ADAP_HWNR & 0x10) \
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FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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} while (0)
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#else
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#define I2C_SET_REG(fld, val) \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_GET_REG(fld, val) \
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do { \
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if (I2C_ADAP_HWNR & 0x10) \
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FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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} while (0)
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#else
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#define I2C_GET_REG(fld, val) \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#endif /* CONFIG_DM_I2C */
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enum {
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I2CINT_ERROR_EV = BIT(13),
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I2CINT_TRANSMIT_EV = BIT(14),
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@ -91,23 +55,13 @@ enum {
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I2COP_READ = 1,
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};
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#if CONFIG_IS_ENABLED(DM_I2C)
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static int wait_for_int(struct udevice *dev, int read)
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#else
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static int wait_for_int(bool read)
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#endif
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{
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u16 val;
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uint ctr = 0;
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct ihs_i2c_priv *priv = dev_get_priv(dev);
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#endif
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_get(priv->map, interrupt_status, &val);
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#else
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I2C_GET_REG(interrupt_status, &val);
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#endif
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/* Wait until error or receive/transmit interrupt was raised */
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while (!(val & (I2CINT_ERROR_EV
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| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
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@ -116,40 +70,24 @@ static int wait_for_int(bool read)
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debug("%s: timed out\n", __func__);
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return -ETIMEDOUT;
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_get(priv->map, interrupt_status, &val);
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#else
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I2C_GET_REG(interrupt_status, &val);
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#endif
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}
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return (val & I2CINT_ERROR_EV) ? -EIO : 0;
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
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uchar *buffer, int len, int read, bool is_last)
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#else
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static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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bool is_last)
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#endif
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{
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u16 val;
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u16 data;
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int res;
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct ihs_i2c_priv *priv = dev_get_priv(dev);
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#endif
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/* Clear interrupt status */
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data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_set(priv->map, interrupt_status, data);
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ihs_i2c_get(priv->map, interrupt_status, &val);
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#else
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I2C_SET_REG(interrupt_status, data);
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I2C_GET_REG(interrupt_status, &val);
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#endif
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/* If we want to write and have data, write the bytes to the mailbox */
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if (!read && len) {
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@ -157,11 +95,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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if (len > 1)
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val |= buffer[1] << 8;
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_set(priv->map, write_mailbox_ext, val);
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#else
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I2C_SET_REG(write_mailbox_ext, val);
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#endif
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}
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data = I2CMB_NATIVE
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@ -170,17 +104,9 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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| ((len > 1) ? I2CMB_2BYTE : 0)
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| (is_last ? 0 : I2CMB_HOLD_BUS);
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_set(priv->map, write_mailbox, data);
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#else
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I2C_SET_REG(write_mailbox, data);
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#endif
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#if CONFIG_IS_ENABLED(DM_I2C)
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res = wait_for_int(dev, read);
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#else
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res = wait_for_int(read);
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#endif
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if (res) {
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if (res == -ETIMEDOUT)
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debug("%s: time out while waiting for event\n", __func__);
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@ -190,11 +116,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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/* If we want to read, get the bytes from the mailbox */
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if (read) {
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#if CONFIG_IS_ENABLED(DM_I2C)
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ihs_i2c_get(priv->map, read_mailbox_ext, &val);
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#else
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I2C_GET_REG(read_mailbox_ext, &val);
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#endif
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buffer[0] = val & 0xff;
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if (len > 1)
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buffer[1] = val >> 8;
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@ -203,12 +125,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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return 0;
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
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#else
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static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
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int read)
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#endif
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{
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int res;
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@ -216,13 +133,8 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
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int transfer = min(len, 2);
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bool is_last = len <= transfer;
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#if CONFIG_IS_ENABLED(DM_I2C)
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res = ihs_i2c_transfer(dev, chip, data, transfer, read,
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hold_bus ? false : is_last);
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#else
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res = ihs_i2c_transfer(chip, data, transfer, read,
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hold_bus ? false : is_last);
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#endif
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if (res)
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return res;
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@ -233,27 +145,14 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
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return 0;
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
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bool hold_bus)
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#else
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static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
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#endif
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{
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#if CONFIG_IS_ENABLED(DM_I2C)
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return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
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#else
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return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
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#endif
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
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int alen, uchar *buffer, int len, int read)
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#else
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static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
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int alen, uchar *buffer, int len, int read)
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#endif
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{
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int res;
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@ -261,23 +160,13 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
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if (len <= 0)
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return -EINVAL;
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#if CONFIG_IS_ENABLED(DM_I2C)
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res = ihs_i2c_address(dev, chip, addr, alen, len);
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#else
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res = ihs_i2c_address(chip, addr, alen, len);
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#endif
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if (res)
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return res;
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#if CONFIG_IS_ENABLED(DM_I2C)
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return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
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#else
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return ihs_i2c_send_buffer(chip, buffer, len, false, read);
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#endif
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}
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#if CONFIG_IS_ENABLED(DM_I2C)
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int ihs_i2c_probe(struct udevice *bus)
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{
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struct ihs_i2c_priv *priv = dev_get_priv(bus);
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@ -358,120 +247,3 @@ U_BOOT_DRIVER(i2c_ihs) = {
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.priv_auto = sizeof(struct ihs_i2c_priv),
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.ops = &ihs_i2c_ops,
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};
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#else /* CONFIG_DM_I2C */
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static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/*
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* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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}
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static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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uchar buffer[2];
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int res;
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res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
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if (res)
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return res;
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return 0;
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}
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static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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put_unaligned_le32(addr, addr_bytes);
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return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
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I2COP_READ);
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}
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static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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put_unaligned_le32(addr, addr_bytes);
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return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
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I2COP_WRITE);
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}
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static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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if (speed != adap->speed)
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return -EINVAL;
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return speed;
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}
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/*
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* Register IHS i2c adapters
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*/
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#ifdef CONFIG_SYS_I2C_IHS_CH0
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U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0,
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CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0_1,
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CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH1
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U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH2
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U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2,
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CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2_1,
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CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH3
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U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3,
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CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3_1,
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CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
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#endif
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#endif
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#endif /* CONFIG_DM_I2C */
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