leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Browse Source
This commit is contained in:
Albert ARIBAUD 2013-12-06 16:54:42 +01:00
commit 375a4496ff
16 changed files with 304 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -1410,7 +1410,8 @@ void set_mmc_clk(int dev_index, unsigned int div)
else {
if (proid_is_exynos4412())
exynos4x12_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
else
exynos4_set_mmc_clk(dev_index, div);
}
}

2
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
printf("SDMMC device %d not implemented\n", peripheral);
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);

126
arch/arm/cpu/armv7/exynos/spl_boot.c
View File

@ -10,8 +10,11 @@
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/dmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/spl.h>
#include <asm/arch/spi.h>
#include "common_setup.h"
#include "clock_init.h"
@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z)
}
#endif
#ifdef CONFIG_SPI_BOOTING
static void spi_rx_tx(struct exynos_spi *regs, int todo,
void *dinp, void const *doutp, int i)
{
uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
int rx_lvl, tx_lvl;
uint out_bytes, in_bytes;
out_bytes = todo;
in_bytes = todo;
setbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
while (in_bytes) {
uint32_t spi_sts;
int temp;
spi_sts = readl(&regs->spi_sts);
rx_lvl = ((spi_sts >> 15) & 0x7f);
tx_lvl = ((spi_sts >> 6) & 0x7f);
while (tx_lvl < 32 && out_bytes) {
temp = 0xffffffff;
writel(temp, &regs->tx_data);
out_bytes -= 4;
tx_lvl += 4;
}
while (rx_lvl >= 4 && in_bytes) {
temp = readl(&regs->rx_data);
if (rxp)
*rxp++ = temp;
in_bytes -= 4;
rx_lvl -= 4;
}
}
}
/*
* Copy uboot from spi flash to RAM
*
* @parma uboot_size size of u-boot to copy
* @param uboot_addr address in u-boot to copy
*/
static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
{
int upto, todo;
int i, timeout = 100;
struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* set the spi1 GPIO */
exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
/* set pktcnt and enable it */
writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
/* set FB_CLK_SEL */
writel(SPI_FB_DELAY_180, &regs->fb_clk);
/* set CH_WIDTH and BUS_WIDTH as word */
setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
SPI_MODE_BUS_WIDTH_WORD);
clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
/* clear rx and tx channel if set priveously */
clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
SPI_RX_BYTE_SWAP |
SPI_RX_HWORD_SWAP);
/* do a soft reset */
setbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
/* now set rx and tx channel ON */
setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
/* Send read instruction (0x3h) followed by a 24 bit addr */
writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
/* waiting for TX done */
while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
if (!timeout) {
debug("SPI TIMEOUT\n");
break;
}
timeout--;
}
for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
todo = min(uboot_size - upto, (1 << 15));
spi_rx_tx(regs, todo, (void *)(uboot_addr),
(void *)(SPI_FLASH_UBOOT_POS), i);
}
setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
/*
* Let put controller mode to BYTE as
* SPI driver does not support WORD mode yet
*/
clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
SPI_MODE_BUS_WIDTH_WORD);
writel(0, &regs->swap_cfg);
/*
* Flush spi tx, rx fifos and reset the SPI controller
* and clear rx/tx channel
*/
clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
}
#endif
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@ -70,6 +188,9 @@ void copy_uboot_to_ram(void)
u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
u32 offset = 0, size = 0;
#ifdef CONFIG_SPI_BOOTING
struct spl_machine_param *param = spl_get_machine_params();
#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
void (*end_bootop_from_emmc)(void);
@ -91,9 +212,8 @@ void copy_uboot_to_ram(void)
switch (bootmode) {
#ifdef CONFIG_SPI_BOOTING
case BOOT_MODE_SERIAL:
offset = SPI_FLASH_UBOOT_POS;
size = CONFIG_BL2_SIZE;
copy_bl2 = get_irom_func(SPI_INDEX);
/* Customised function to copy u-boot from SF */
exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
break;
#endif
case BOOT_MODE_MMC:

4
arch/arm/include/asm/arch-exynos/dwmmc.h
View File

@ -6,10 +6,6 @@
*/
#define DWMCI_CLKSEL 0x09C
#define DWMCI_SHIFT_0 0x0
#define DWMCI_SHIFT_1 0x1
#define DWMCI_SHIFT_2 0x2
#define DWMCI_SHIFT_3 0x3
#define DWMCI_SET_SAMPLE_CLK(x) (x)
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)

2
arch/arm/include/asm/arch-exynos/mmc.h
View File

@ -55,7 +55,7 @@
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
static inline int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);

2
arch/arm/include/asm/arch-exynos/power.h
View File

@ -16,7 +16,7 @@ struct exynos4_power {
unsigned int gnss_rtc_out_ctrl;
unsigned char res2[0x1ec];
unsigned int system_power_down_ctrl;
unsigned char res3[0x1];
unsigned int res3;
unsigned int system_power_down_option;
unsigned char res4[0x1f4];
unsigned int swreset;

1
arch/arm/include/asm/arch-exynos/spi.h
View File

@ -30,6 +30,7 @@ struct exynos_spi {
#define EXYNOS_SPI_MAX_FREQ 50000000
#define SPI_TIMEOUT_MS 10
#define SF_READ_DATA_CMD 0x3
/* SPI_CHCFG */
#define SPI_CH_HS_EN (1 << 6)

2
arch/arm/include/asm/arch-s5pc1xx/mmc.h
View File

@ -55,7 +55,7 @@
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
static inline int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);

11
board/samsung/trats/trats.c
View File

@ -501,6 +501,17 @@ int board_usb_init(int index, enum usb_init_type init)
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}
#ifdef CONFIG_USB_CABLE_CHECK
int usb_cable_connected(void)
{
struct pmic *muic = pmic_get("MAX8997_MUIC");
if (!muic)
return 0;
return !!muic->chrg->chrg_type(muic);
}
#endif
#endif
static void pmic_reset(void)

108
board/samsung/trats2/trats2.c
View File

@ -25,6 +25,9 @@
#include <power/max77693_fg.h>
#include <libtizen.h>
#include <errno.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
@ -40,7 +43,7 @@ static void check_hw_revision(void)
int modelrev = 0;
int i;
gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* GPM1[1:0]: MODEL_REV[1:0]
@ -90,7 +93,7 @@ static inline u32 get_model_rev(void)
static void board_external_gpio_init(void)
{
gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* some pins which in alive block are connected with external pull-up
@ -115,8 +118,8 @@ static void board_external_gpio_init(void)
#ifdef CONFIG_SYS_I2C_INIT_BOARD
static void board_init_i2c(void)
{
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_7 */
s5p_gpio_direction_output(&gpio1->d0, 2, 1);
@ -147,7 +150,7 @@ static int pmic_init_max77686(void);
int board_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)EXYNOS4X12_POWER_BASE;
(struct exynos4_power *)samsung_get_base_power();
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@ -254,7 +257,7 @@ int board_mmc_init(bd_t *bis)
{
int err0, err2 = 0;
gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio2->k0, 2, 1);
@ -308,6 +311,95 @@ int board_mmc_init(bd_t *bis)
return err0 & err2;
}
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
int ret = 0;
unsigned int val;
struct pmic *p, *p_pmic, *p_muic;
p_pmic = pmic_get("MAX77686_PMIC");
if (!p_pmic)
return -ENODEV;
if (pmic_probe(p_pmic))
return -1;
p_muic = pmic_get("MAX77693_MUIC");
if (!p_muic)
return -ENODEV;
if (pmic_probe(p_muic))
return -1;
if (on) {
ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
if (ret)
return -1;
p = pmic_get("MAX77693_PMIC");
if (!p)
return -ENODEV;
if (pmic_probe(p))
return -1;
/* SAFEOUT */
ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
if (ret)
return -1;
val |= MAX77693_ENSAFEOUT1;
ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
if (ret)
return -1;
/* PATH: USB */
ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
MAX77693_MUIC_CTRL1_DN1DP2);
} else {
ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
if (ret)
return -1;
/* PATH: UART */
ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
MAX77693_MUIC_CTRL1_UT1UR2);
}
if (ret)
return -1;
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}
#ifdef CONFIG_USB_CABLE_CHECK
int usb_cable_connected(void)
{
struct pmic *muic = pmic_get("MAX77693_MUIC");
if (!muic)
return 0;
return !!muic->chrg->chrg_type(muic);
}
#endif
#endif
static int pmic_init_max77686(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
@ -421,7 +513,7 @@ void exynos_lcd_power_on(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* LCD_2.2V_EN: GPC0[1] */
s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
@ -435,7 +527,7 @@ void exynos_lcd_power_on(void)
void exynos_reset_lcd(void)
{
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* reset lcd */
s5p_gpio_direction_output(&gpio1->f2, 1, 0);

5
drivers/usb/gadget/regs-otg.h
View File

@ -226,6 +226,11 @@ struct s3c_usbotg_reg {
#define CLK_SEL_12MHZ (0x2 << 0)
#define CLK_SEL_48MHZ (0x0 << 0)
#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
/* Device Configuration Register DCFG */
#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)

9
drivers/usb/gadget/s3c_udc_otg.c
View File

@ -167,8 +167,13 @@ void otg_phy_init(struct s3c_udc *dev)
writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
&~FORCE_SUSPEND_0), &phy->phypwr);
writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
if (s5p_cpu_id == 0x4412)
writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
&phy->phyclk); /* PLL 24Mhz */
else
writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
| PHY_SW_RST0, &phy->rstcon);

4
include/configs/arndale.h
View File

@ -198,10 +198,6 @@
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
#define CONFIG_SPI_BOOTING
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_PART

25
include/configs/exynos5250-dt.h
View File

@ -157,6 +157,7 @@
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* specific .lds file */
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
@ -255,7 +256,7 @@
#define CONFIG_DRIVER_S3C24X0_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_MAX_I2C_NUM 8
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_I2C_EDID
/* PMIC */
@ -266,6 +267,7 @@
/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
@ -290,27 +292,6 @@
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
#endif
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_ENV_SPI_MAX_HZ 50000000
#endif
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X

1
include/configs/trats.h
View File

@ -308,6 +308,7 @@
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_CABLE_CHECK
/* LCD */
#define CONFIG_EXYNOS_FB

68
include/configs/trats2.h
View File

@ -20,8 +20,6 @@
#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
#define CONFIG_TIZEN /* TIZEN lib */
#define PLATFORM_NO_UNALIGNED
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
@ -65,10 +63,9 @@
#define CONFIG_DISPLAY_CPUINFO
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
#include <asm/sizes.h>
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
#define CONFIG_SERIAL2
@ -100,6 +97,7 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
#define CONFIG_CMD_GPT
#define CONFIG_CMD_PMIC
@ -113,6 +111,23 @@
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_THOR_FUNCTION
/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
#define CONFIG_G_DNL_MANUFACTURER "Samsung"
/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
#undef CONFIG_CMD_NET
@ -136,25 +151,29 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
#define PARTS_BOOTLOADER "u-boot"
#define PARTS_CSA "csa"
#define PARTS_BOOT "boot"
#define PARTS_MODEM "modem"
#define PARTS_CSC "csc"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
#define PARTS_CSC "csc"
#define PARTS_UMS "ums"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
"name="PARTS_BOOTLOADER",size=60MiB," \
"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
"name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
"name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
"name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
"u-boot mmc 80 800;" \
"uImage ext4 0 2;" \
"exynos4412-trats2.dtb ext4 0 2;" \
""PARTS_ROOT" part 0 5\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
@ -178,15 +197,16 @@
"rootfstype=ext4\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
"kernelname=uImage\0" \
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
"0x40007FC0 ${kernelname}\0" \
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
"${kernelname}\0" \
"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
"${fdtfile}\0" \
"mmcdev=0\0" \
"mmcdev=CONFIG_MMC_DEFAULT_DEV\0" \
"mmcbootpart=2\0" \
"mmcrootpart=5\0" \
"opts=always_resume=1\0" \
"partitions=" PARTS_DEFAULT \
"dfu_alt_info=" CONFIG_DFU_ALT \
"uartpath=ap\0" \
"usbpath=ap\0" \
"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
@ -233,8 +253,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
@ -293,6 +311,11 @@
#define CONFIG_POWER_MUIC_MAX77693
#define CONFIG_POWER_FG_MAX77693
#define CONFIG_POWER_BATTERY_TRATS2
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_CABLE_CHECK
/* LCD */
#define CONFIG_EXYNOS_FB
@ -305,6 +328,9 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1