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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2014-07-29 09:41:35 -04:00
commit 362f16b1e9
154 changed files with 6536 additions and 1737 deletions
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6
Makefile
View File

@ -915,6 +915,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
u-boot-nand.gph: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff

2
arch/arm/config.mk
View File

@ -113,7 +113,7 @@ endif
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
endif
ifdef CONFIG_OF_EMBED

5
arch/arm/cpu/armv7/Makefile
View File

@ -21,6 +21,11 @@ endif
ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
obj-y += nonsec_virt.o
obj-y += virt-v7.o
obj-y += virt-dt.o
endif
ifneq ($(CONFIG_ARMV7_PSCI),)
obj-y += psci.o
endif
obj-$(CONFIG_KONA) += kona-common/

5
arch/arm/cpu/armv7/keystone/Makefile
View File

@ -8,9 +8,12 @@
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += keystone_nav.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o
obj-y += keystone.o

101
arch/arm/cpu/armv7/keystone/clock-k2e.c Normal file
View File

@ -0,0 +1,101 @@
/*
* Keystone2: get clk rate for K2E
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case DDR3_PLL:
ret = external_clk[ddr3_clk];
reg = KS2_DDR3APLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}

113
arch/arm/cpu/armv7/keystone/clock-k2hk.c Normal file
View File

@ -0,0 +1,113 @@
/*
* Keystone2: get clk rate for K2HK
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = KS2_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}

154
arch/arm/cpu/armv7/keystone/clock.c
View File

@ -8,9 +8,6 @@
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
}
}
struct pll_regs {
u32 reg0, reg1;
};
static const struct pll_regs pll_regs[] = {
[CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
[PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
[TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
[DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
[DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
};
/* Fout = Fref * NF(mult) / NR(prediv) / OD */
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(K2HK_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = K2HK_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = K2HK_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = K2HK_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = K2HK_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}
void init_pll(const struct pll_init_data *data)
{
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_read(data->pll, secctl);
if (tmp & (PLLCTL_BYPASS)) {
setbits_le32(pll_regs[data->pll].reg1,
setbits_le32(keystone_pll_regs[data->pll].reg1,
BIT(MAIN_ENSAT_OFFSET));
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
(pllm << 6));
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLLM_MULT_HI_SMASK, (pllm << 6));
/* Set the BWADJ (12 bit field) */
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLL_BWADJ_LO_SMASK,
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
PLL_BWADJ_HI_MASK,
(tmp_ctl >> 8));
/*
* Set the pll divider (6 bit field) *
* PLLD[5:0] is located in MAINPLLCTL0
*/
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLL_DIV_MASK, plld);
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
#ifndef CONFIG_SOC_K2E
} else if (data->pll == TETRIS_PLL) {
bwadj = pllm >> 1;
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
setbits_le32(pll_regs[data->pll].reg1 ,
setbits_le32(keystone_pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
/*
@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
(pllm << 6) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
__raw_writel(tmp, pll_regs[data->pll].reg0);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
__raw_writel(tmp, pll_regs[data->pll].reg1);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/*
* 5 Wait for at least 5 us based on the reference
* clock (PLL reset time)
@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
sdelay(21000); /* Wait for a minimum of 7 us*/
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
/*
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
* (PLL lock time)
*/
sdelay(105000);
/* 8 disable bypass */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
#endif
} else {
setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
* process keeps state of Bypass bit while programming
* all other DDR PLL settings
*/
tmp = __raw_readl(pll_regs[data->pll].reg0);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
/*
@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
(pllm << PLL_MULT_SHIFT) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT);
__raw_writel(tmp, pll_regs[data->pll].reg0);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
__raw_writel(tmp, pll_regs[data->pll].reg1);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
tmp = PLL_PLLRST;
/* Set RESET bit = 1 */
setbits_le32(pll_regs[data->pll].reg1, tmp);
setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
/* Wait for a minimum of 7 us*/
sdelay(21000);
/* Clear RESET bit */
clrbits_le32(pll_regs[data->pll].reg1, tmp);
clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
sdelay(105000);
/* clear BYPASS (Enable PLL Mode) */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
sdelay(21000); /* Wait for a minimum of 7 us*/
}

31
arch/arm/cpu/armv7/keystone/cmd_clock.c
View File

@ -14,10 +14,10 @@
#include <asm/arch/psc_defs.h>
struct pll_init_data cmd_pll_data = {
.pll = MAIN_PLL,
.pll_m = 16,
.pll_d = 1,
.pll_od = 2,
.pll = MAIN_PLL,
.pll_m = 16,
.pll_d = 1,
.pll_od = 2,
};
int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (strncmp(argv[1], "pa", 2) == 0)
cmd_pll_data.pll = PASS_PLL;
#ifndef CONFIG_SOC_K2E
else if (strncmp(argv[1], "arm", 3) == 0)
cmd_pll_data.pll = TETRIS_PLL;
#endif
#ifdef CONFIG_SOC_K2HK
else if (strncmp(argv[1], "ddr3a", 5) == 0)
cmd_pll_data.pll = DDR3A_PLL;
else if (strncmp(argv[1], "ddr3b", 5) == 0)
cmd_pll_data.pll = DDR3B_PLL;
#else
else if (strncmp(argv[1], "ddr3", 4) == 0)
cmd_pll_data.pll = DDR3_PLL;
#endif
else
goto pll_cmd_usage;
@ -51,11 +58,20 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
#ifdef CONFIG_SOC_K2HK
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
);
#endif
#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|ddr3> <mult> <div> <OD>\n"
);
#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -79,7 +95,12 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
#ifdef CONFIG_SOC_K2HK
"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
#endif
#ifdef CONFIG_SOC_K2E
"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
#endif
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

25
arch/arm/cpu/armv7/keystone/ddr3.c
View File

@ -7,10 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <common.h>
#include <asm/arch/ddr3.h>
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
}
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
void ddr3_reset_ddrphy(void)
{
u32 tmp;
/* Assert DDR3A PHY reset */
tmp = readl(KS2_DDR3APLLCTL1);
tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
writel(tmp, KS2_DDR3APLLCTL1);
/* wait 10us to catch the reset */
udelay(10);
/* Release DDR3A PHY reset */
tmp = readl(KS2_DDR3APLLCTL1);
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, KS2_DDR3APLLCTL1);
}

16
arch/arm/cpu/armv7/keystone/init.c
View File

@ -10,13 +10,14 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
void chip_configuration_unlock(void)
{
__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
int arch_cpu_init(void)
@ -24,11 +25,12 @@ int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
#ifdef CONFIG_SOC_K2HK
share_all_segments(8);
share_all_segments(9);
share_all_segments(10); /* QM PDSP */
share_all_segments(11); /* PCIE */
msmc_share_all_segments(8); /* TETRIS */
msmc_share_all_segments(9); /* NETCP */
msmc_share_all_segments(10); /* QM PDSP */
msmc_share_all_segments(11); /* PCIE 0 */
#ifdef CONFIG_SOC_K2E
msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*

87
arch/arm/cpu/armv7/keystone/keystone.c Normal file
View File

@ -0,0 +1,87 @@
/*
* Keystone EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mon.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/hardware.h>
/**
* cpu_to_bus - swap bytes of the 32-bit data if the device is BE
* @ptr - array of data
* @length - lenght of data array
*/
int cpu_to_bus(u32 *ptr, u32 length)
{
u32 i;
if (!(readl(KS2_DEVSTAT) & 0x1))
for (i = 0; i < length; i++, ptr++)
*ptr = cpu_to_be32(*ptr);
return 0;
}
static int turn_off_myself(void)
{
printf("Turning off ourselves\r\n");
mon_power_off(0);
psc_disable_module(KS2_LPSC_TETRIS);
psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
asm volatile ("isb\n"
"dsb\n"
"wfi\n");
printf("What! Should not see that\n");
return 0;
}
static void turn_off_all_dsps(int num_dsps)
{
int i;
for (i = 0; i < num_dsps; i++) {
if (psc_disable_module(i + KS2_LPSC_GEM_0))
printf("Cannot disable module for #%d DSP", i);
if (psc_disable_domain(i + 8))
printf("Cannot disable domain for #%d DSP", i);
}
}
int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return turn_off_myself();
}
U_BOOT_CMD(
killme, 1, 0, do_killme_cmd,
"turn off main ARM core",
"turn off main ARM core. Should not live after that :(\n"
);
int misc_init_r(void)
{
char *env;
long ks2_debug = 0;
env = getenv("ks2_debug");
if (env)
ks2_debug = simple_strtol(env, NULL, 0);
if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
turn_off_all_dsps(KS2_NUM_DSPS);
return 0;
}

6
arch/arm/cpu/armv7/keystone/msmc.c
View File

@ -8,7 +8,7 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
@ -56,9 +56,9 @@ struct msms_regs {
};
void share_all_segments(int priv_id)
void msmc_share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {

42
arch/arm/cpu/armv7/keystone/psc.c
View File

@ -16,10 +16,6 @@
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
#ifdef CONFIG_SOC_K2HK
#define DEVICE_PSC_BASE K2HK_PSC_BASE
#endif
int psc_delay(void)
{
udelay(10);
@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
do {
ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
/* Get the power domain associated with the module number */
domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
/* Set the reset isolation bit */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
u32 pdctl;
u32 ptcmd;
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}

8
arch/arm/cpu/armv7/keystone/spl.c
View File

@ -18,10 +18,18 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_K2HK_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
#endif
#ifdef CONFIG_K2E_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_800,
};
#endif
void spl_init_keystone_plls(void)
{

166
arch/arm/cpu/armv7/nonsec_virt.S
View File

@ -10,10 +10,13 @@
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/armv7.h>
#include <asm/proc-armv/ptrace.h>
.arch_extension sec
.arch_extension virt
.pushsection ._secure.text, "ax"
.align 5
/* the vector table for secure state and HYP mode */
_monitor_vectors:
@ -22,43 +25,95 @@ _monitor_vectors:
adr pc, _secure_monitor
.word 0
.word 0
adr pc, _hyp_trap
.word 0
.word 0
.word 0
.macro is_cpu_virt_capable tmp
mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
.endm
/*
* secure monitor handler
* U-boot calls this "software interrupt" in start.S
* This is executed on a "smc" instruction, we use a "smc #0" to switch
* to non-secure state.
* We use only r0 and r1 here, due to constraints in the caller.
* r0, r1, r2: passed to the callee
* ip: target PC
*/
_secure_monitor:
mrc p15, 0, r1, c1, c1, 0 @ read SCR
bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
orr r1, r1, #0x31 @ enable NS, AW, FW bits
#ifdef CONFIG_ARMV7_PSCI
ldr r5, =_psci_vectors @ Switch to the next monitor
mcr p15, 0, r5, c12, c0, 1
isb
#ifdef CONFIG_ARMV7_VIRT
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
orreq r1, r1, #0x100 @ allow HVC instruction
@ Obtain a secure stack, and configure the PSCI backend
bl psci_arch_init
#endif
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
@ FIQ preserved for secure mode
mov r6, #SVC_MODE @ default mode is SVC
is_cpu_virt_capable r4
#ifdef CONFIG_ARMV7_VIRT
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
#endif
movs pc, lr @ return to non-secure SVC
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
isb
_hyp_trap:
mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
mov pc, lr @ do no switch modes, but
@ return to caller
bne 1f
@ Reset CNTVOFF to 0 before leaving monitor mode
mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
movne r4, #0
mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
1:
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
tst lr, #1 @ Check for Thumb PC
orrne ip, ip, #T_BIT @ Set T if Thumb
orr ip, ip, r6 @ Slot target mode in
msr spsr_cxfs, ip @ Set full SPSR
movs pc, lr @ ERET to non-secure
ENTRY(_do_nonsec_entry)
mov ip, r0
mov r0, r1
mov r1, r2
mov r2, r3
smc #0
ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits
#endif
.endm
.macro get_gicd_addr addr
get_cbar_addr \addr
add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
.endm
.macro get_gicc_addr addr, tmp
get_cbar_addr \addr
is_cpu_virt_capable \tmp
movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
add \addr, \addr, \tmp
.endm
#ifndef CONFIG_ARMV7_PSCI
/*
* Secondary CPUs start here and call the code for the core specific parts
* of the non-secure and HYP mode transition. The GIC distributor specific
@ -66,31 +121,21 @@ _hyp_trap:
* Then they go back to wfi and wait to be woken up by the kernel again.
*/
ENTRY(_smp_pen)
mrs r0, cpsr
orr r0, r0, #0xc0
msr cpsr, r0 @ disable interrupts
ldr r1, =_start
mcr p15, 0, r1, c12, c0, 0 @ set VBAR
cpsid i
cpsid f
bl _nonsec_init
mov r12, r0 @ save GICC address
#ifdef CONFIG_ARMV7_VIRT
bl _switch_to_hyp
#endif
ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
str r1, [r12, #GICC_EOIR] @ signal end of interrupt
adr r0, _smp_pen @ do not use this address again
b smp_waitloop @ wait for IPIs, board specific
ENDPROC(_smp_pen)
#endif
/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
* 2. allow coprocessor access in non-secure modes
* 3. switch the cpu mode (by calling "smc #0")
*
* Called from smp_pen by secondary cores and directly by the BSP.
* Do not assume that the stack is available and only use registers
@ -100,38 +145,23 @@ ENDPROC(_smp_pen)
* though, but we check this in C before calling this function.
*/
ENTRY(_nonsec_init)
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, r2, c15, c0, 0 @ read CBAR
bfc r2, #0, #15 @ clear reserved bits
#endif
add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
get_gicd_addr r3
mvn r1, #0 @ all bits to 1
str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
mrc p15, 0, r0, c0, c0, 0 @ read MIDR
ldr r1, =MIDR_PRIMARY_PART_MASK
and r0, r0, r1 @ mask out variant and revision
get_gicc_addr r3, r1
ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
cmp r0, r1 @ check for Cortex-A7
ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
cmpne r0, r1 @ check for Cortex-A15
movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
add r3, r2, r1 @ r3 = GIC CPU i/f addr
mov r1, #1 @ set GICC_CTLR[enable]
mov r1, #3 @ Enable both groups
str r1, [r3, #GICC_CTLR] @ and clear all other bits
mov r1, #0xff
str r1, [r3, #GICC_PMR] @ set priority mask register
mrc p15, 0, r0, c1, c1, 2
movw r1, #0x3fff
movt r1, #0x0006
mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
movt r1, #0x0004
orr r0, r0, r1
mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
/* The CNTFRQ register of the generic timer needs to be
* programmed in secure state. Some primary bootloaders / firmware
@ -149,21 +179,9 @@ ENTRY(_nonsec_init)
adr r1, _monitor_vectors
mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
isb
smc #0 @ call into MONITOR mode
mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
mov r1, #1
str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
add r2, r2, #GIC_DIST_OFFSET
str r1, [r2, #GICD_CTLR] @ allow private interrupts
mov r0, r3 @ return GICC address
bx lr
ENDPROC(_nonsec_init)
@ -175,18 +193,10 @@ ENTRY(smp_waitloop)
ldr r1, [r1]
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov pc, r1
mov r0, r1
b _do_nonsec_entry
ENDPROC(smp_waitloop)
.weak smp_waitloop
#endif
ENTRY(_switch_to_hyp)
mov r0, lr
mov r1, sp @ save SVC copy of LR and SP
isb
hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
mov sp, r1
mov lr, r0 @ restore SVC copy of LR and SP
bx lr
ENDPROC(_switch_to_hyp)
.popsection

3
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -123,7 +123,8 @@ void s_init(void)
hw_data_init();
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
if (warm_reset() &&
(is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
force_emif_self_refresh();
#endif
watchdog_init();

15
arch/arm/cpu/armv7/omap-common/mem-common.c
View File

@ -87,9 +87,13 @@ void gpmc_init(void)
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
#elif defined(CONFIG_NAND)
u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
/* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
/* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
/* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
/* min 16MB */ GPMC_SIZE_16M)));
#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@ -99,8 +103,9 @@ void gpmc_init(void)
M_NAND_GPMC_CONFIG6,
0
};
u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
u32 size = GPMC_SIZE_16M;
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
@ -110,8 +115,8 @@ void gpmc_init(void)
ONENAND_GPMC_CONFIG6,
0
};
u32 base = PISMO1_ONEN_BASE;
u32 size = PISMO1_ONEN_SIZE;
u32 size = GPMC_SIZE_128M;
u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;

139
arch/arm/cpu/armv7/omap3/mem.c
View File

@ -1,139 +0,0 @@
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
ONENAND_GPMC_CONFIG4,
ONENAND_GPMC_CONFIG5,
ONENAND_GPMC_CONFIG6, 0
};
#endif /* CONFIG_CMD_ONENAND */
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in guessing which part
* we are currently using.
*******************************************************/
u32 mem_ok(u32 cs)
{
u32 val1, val2, addr;
u32 pattern = 0x12345678;
addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
writel(0x0, addr + 0x400); /* clear pos A */
writel(pattern, addr); /* pattern to pos B */
writel(0x0, addr + 4); /* remove pattern off the bus */
val1 = readl(addr + 0x400); /* get pos A value */
val2 = readl(addr); /* get val2 */
writel(0x0, addr + 0x400); /* clear pos A */
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
return 0;
else
return 1;
}
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/*
* Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000);
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
const u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
#endif
u32 config = 0;
/* global settings */
writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
config = readl(&gpmc_cfg->config);
config &= (~0xf00);
writel(config, &gpmc_cfg->config);
/*
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x08000000)
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */
gpmc_config = gpmc_m_nand;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
#if defined(CONFIG_CMD_ONENAND)
gpmc_config = gpmc_onenand;
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
}

102
arch/arm/cpu/armv7/psci.S Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright (C) 2013,2014 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl _psci_vectors
_psci_vectors:
b default_psci_vector @ reset
b default_psci_vector @ undef
b _smc_psci @ smc
b default_psci_vector @ pabort
b default_psci_vector @ dabort
b default_psci_vector @ hyp
b default_psci_vector @ irq
b psci_fiq_enter @ fiq
ENTRY(psci_fiq_enter)
movs pc, lr
ENDPROC(psci_fiq_enter)
.weak psci_fiq_enter
ENTRY(default_psci_vector)
movs pc, lr
ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
ENTRY(psci_migrate)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ENDPROC(psci_migrate)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_migrate
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
.word 0
.word 0
_smc_psci:
push {r4-r7,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
bic r4, r7, #1
mcr p15, 0, r4, c1, c1, 0
isb
adr r4, _psci_table
1: ldr r5, [r4] @ Load PSCI function ID
ldr r6, [r4, #4] @ Load target PC
cmp r5, #0 @ If reach the end, bail out
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
beq 2f
cmp r0, r5 @ If not matching, try next entry
addne r4, r4, #8
bne 1b
blx r6 @ Execute PSCI function
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
pop {r4-r7, lr}
movs pc, lr @ Return to the kernel
.popsection

1
arch/arm/cpu/armv7/rmobile/Makefile
View File

@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o

1
arch/arm/cpu/armv7/rmobile/cpu_info.c
View File

@ -53,6 +53,7 @@ static const struct {
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4C, "R8A7794" },
{ 0x0, "CPU" },
};

1513
arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/cpu/armv7/sunxi/Makefile
View File

@ -11,6 +11,8 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_SUN4I) += clock_sun4i.o
obj-$(CONFIG_SUN5I) += clock_sun4i.o
obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
@ -18,6 +20,8 @@ obj-y += cpu_info.o
endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SUN4I) += dram.o
obj-$(CONFIG_SUN5I) += dram.o
obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o

41
arch/arm/cpu/armv7/sunxi/board.c
View File

@ -11,6 +11,7 @@
*/
#include <common.h>
#include <i2c.h>
#include <netdev.h>
#include <miiphy.h>
#include <serial.h>
@ -24,6 +25,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <linux/compiler.h>
#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
@ -47,15 +50,38 @@ u32 spl_boot_mode(void)
int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
return 0;
}
void reset_cpu(ulong addr)
{
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* Set the watchdog for its shortest interval (.5s) and wait */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
while (1) {
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
}
/* do some early init */
@ -72,11 +98,16 @@ void s_init(void)
clock_init();
timer_init();
gpio_init();
i2c_init_board();
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
#endif
}
@ -96,7 +127,15 @@ void enable_caches(void)
*/
int cpu_eth_init(bd_t *bis)
{
int rc;
__maybe_unused int rc;
#ifdef CONFIG_SUNXI_EMAC
rc = sunxi_emac_initialize(bis);
if (rc < 0) {
printf("sunxi: failed to initialize emac\n");
return rc;
}
#endif
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);

3
arch/arm/cpu/armv7/sunxi/clock_sun4i.c
View File

@ -36,8 +36,7 @@ void clock_init_safe(void)
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}

15
arch/arm/cpu/armv7/sunxi/cpu_info.c
View File

@ -13,7 +13,22 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
#ifdef CONFIG_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
#elif defined CONFIG_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
#elif defined CONFIG_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
#endif
return 0;
}
#endif

102
arch/arm/cpu/armv7/sunxi/dram.c
View File

@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void)
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(2);
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
#ifdef CONFIG_SUN4I
struct sunxi_timer_reg *timer =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
u32 reg_val;
writel(0, &timer->cpu_cfg);
reg_val = readl(&timer->cpu_cfg);
if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(2);
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
} else
#endif
{
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(2);
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
}
}
static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
#ifdef CONFIG_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
#else
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
#endif
DRAM_MCR_MODE_EN(0x3) |
0xffc);
}
@ -134,6 +155,26 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
#ifdef CONFIG_SUN5I
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x1031, 0x1031, 0x0735, 0x1035,
0x1035, 0x0731, 0x1031, 0,
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0
#endif
#ifdef CONFIG_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x1031, 0x1031, 0x0735, 0x5031,
0x1035, 0x0731, 0x1031, 0x0735,
0x1035, 0x1031, 0x0731, 0x1035,
0x1031, 0x0301, 0x0301, 0x0731
#endif
#ifdef CONFIG_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
@ -223,22 +264,38 @@ static void mctl_setup_dram_clock(u32 clk)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
#endif
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
/* setup MBUS clock */
reg_val = CCM_MBUS_CTRL_GATE |
#ifdef CONFIG_SUN7I
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
#else /* defined(CONFIG_SUN5I) */
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
#endif
writel(reg_val, &ccm->mbus_clk_cfg);
#endif
/*
* open DRAMC AHB & DLL register clock
* close it first
*/
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
udelay(22);
/* then open it */
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
udelay(22);
}
@ -385,6 +442,13 @@ static void dramc_clock_output_en(u32 on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
#ifdef CONFIG_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
else
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
#endif
}
static const u16 tRFC_table[2][6] = {
@ -420,12 +484,25 @@ unsigned long dramc_init(struct dram_para *para)
/* setup DRAM relative clock */
mctl_setup_dram_clock(para->clock);
#ifdef CONFIG_SUN5I
/* Disable any pad power save control */
writel(0, &dram->ppwrsctl);
#endif
/* reset external DRAM */
#ifndef CONFIG_SUN7I
mctl_ddr3_reset();
#endif
mctl_set_drive();
/* dram clock off */
dramc_clock_output_en(0);
#ifdef CONFIG_SUN4I
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
#endif
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@ -482,6 +559,9 @@ unsigned long dramc_init(struct dram_para *para)
mctl_ddr3_reset();
else
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
#else
/* dram clock on */
dramc_clock_output_en(1);
#endif
udelay(1);
@ -490,6 +570,22 @@ unsigned long dramc_init(struct dram_para *para)
mctl_enable_dllx(para->tpr3);
#ifdef CONFIG_SUN4I
/* set odt impedance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
writel(reg_val, &dram->zqcr0);
#endif
#ifdef CONFIG_SUN4I
/* set I/O configure register */
reg_val = 0x00cc0000;
reg_val |= (para->odt_en) & 0x3;
reg_val |= ((para->odt_en) & 0x3) << 30;
writel(reg_val, &dram->iocr);
#endif
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);

5
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
View File

@ -26,6 +26,11 @@ SECTIONS
*(.data*)
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
. = .;

6
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
View File

@ -27,6 +27,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} > .sram
@ -37,6 +38,11 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;

100
arch/arm/cpu/armv7/virt-dt.c Normal file
View File

@ -0,0 +1,100 @@
/*
* Copyright (C) 2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/armv7.h>
#include <asm/psci.h>
static int fdt_psci(void *fdt)
{
#ifdef CONFIG_ARMV7_PSCI
int nodeoff;
int tmp;
nodeoff = fdt_path_offset(fdt, "/cpus");
if (nodeoff < 0) {
printf("couldn't find /cpus\n");
return nodeoff;
}
/* add 'enable-method = "psci"' to each cpu node */
for (tmp = fdt_first_subnode(fdt, nodeoff);
tmp >= 0;
tmp = fdt_next_subnode(fdt, tmp)) {
const struct fdt_property *prop;
int len;
prop = fdt_get_property(fdt, tmp, "device_type", &len);
if (!prop)
continue;
if (len < 4)
continue;
if (strcmp(prop->data, "cpu"))
continue;
fdt_setprop_string(fdt, tmp, "enable-method", "psci");
}
nodeoff = fdt_path_offset(fdt, "/psci");
if (nodeoff < 0) {
nodeoff = fdt_path_offset(fdt, "/");
if (nodeoff < 0)
return nodeoff;
nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
if (nodeoff < 0)
return nodeoff;
}
tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
if (tmp)
return tmp;
#endif
return 0;
}
int armv7_update_dt(void *fdt)
{
#ifndef CONFIG_ARMV7_SECURE_BASE
/* secure code lives in RAM, keep it alive */
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
__secure_end - __secure_start);
#endif
return fdt_psci(fdt);
}

76
arch/arm/cpu/armv7/virt-v7.c
View File

@ -13,17 +13,10 @@
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
#include <asm/secure.h>
unsigned long gic_dist_addr;
static unsigned int read_cpsr(void)
{
unsigned int reg;
asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
return reg;
}
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void)
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#else
unsigned midr;
unsigned periphbase;
/* check whether we are an Cortex-A15 or A7.
* The actual HYP switch should work with all CPUs supporting
* the virtualization extension, but we need the GIC address,
* which we know only for sure for those two CPUs.
*/
asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
switch (midr & MIDR_PRIMARY_PART_MASK) {
case MIDR_CORTEX_A9_R0P1:
case MIDR_CORTEX_A15_R0P0:
case MIDR_CORTEX_A7_R0P0:
break;
default:
printf("nonsec: could not determine GIC address.\n");
return -1;
}
/* get the GIC base address from the CBAR register */
asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void)
#endif
}
static void relocate_secure_section(void)
{
#ifdef CONFIG_ARMV7_SECURE_BASE
size_t sz = __secure_end - __secure_start;
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
CONFIG_ARMV7_SECURE_BASE + sz + 1);
invalidate_icache_all();
#endif
}
static void kick_secondary_cpus_gic(unsigned long gicdaddr)
{
/* kick all CPUs (except this one) by writing to GICD_SGIR */
@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void)
kick_secondary_cpus_gic(gic_dist_addr);
}
int armv7_switch_hyp(void)
{
unsigned int reg;
/* check whether we are in HYP mode already */
if ((read_cpsr() & 0x1f) == 0x1a) {
debug("CPU already in HYP mode\n");
return 0;
}
/* check whether the CPU supports the virtualization extensions */
reg = read_id_pfr1();
if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
printf("HYP mode: Virtualization extensions not implemented.\n");
return -1;
}
/* call the HYP switching code on this CPU also */
_switch_to_hyp();
if ((read_cpsr() & 0x1F) != 0x1a) {
printf("HYP mode: switch not successful.\n");
return -1;
}
return 0;
}
int armv7_switch_nonsec(void)
int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
@ -147,11 +107,13 @@ int armv7_switch_nonsec(void)
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
#ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
smp_kick_all_cpus();
#endif
/* call the non-sec switching code on this CPU also */
_nonsec_init();
relocate_secure_section();
secure_ram_addr(_nonsec_init)();
return 0;
}

4
arch/arm/cpu/armv7/zynq/ddrc.c
View File

@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
/* ECC is enabled when memory is in 16bit mode and it is enabled */
if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
puts("Memory: ECC enabled\n");
puts("ECC enabled ");
/*
* Clear the first 1MB because it is not initialized from
* first stage bootloader. To get ECC to work all memory has
@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
*/
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("Memory: ECC disabled\n");
puts("ECC disabled ");
}
}

30
arch/arm/cpu/u-boot.lds
View File

@ -7,6 +7,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
@ -23,6 +25,34 @@ SECTIONS
*(.text*)
}
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
#ifndef CONFIG_ARMV7_SECURE_BASE
#define CONFIG_ARMV7_SECURE_BASE
#endif
.__secure_start : {
. = ALIGN(0x1000);
*(.__secure_start)
}
.secure_text CONFIG_ARMV7_SECURE_BASE :
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
{
*(._secure.text)
}
. = LOADADDR(.__secure_start) +
SIZEOF(.__secure_start) +
SIZEOF(.secure_text);
__secure_end_lma = .;
.__secure_end : AT(__secure_end_lma) {
*(.__secure_end)
LONG(0x1d1071c); /* Must output something to reset LMA */
}
#endif
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }

4
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -33,11 +33,7 @@
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
#define MT47H128M16RT25E_WR_DQS 0x00
#define MT47H128M16RT25E_PHY_WRLVL 0x00
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B

7
arch/arm/include/asm/arch-am33xx/mem.h
View File

@ -59,13 +59,6 @@
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
#endif /* endif _MEM_H_ */

68
arch/arm/include/asm/arch-keystone/clock-k2e.h Normal file
View File

@ -0,0 +1,68 @@
/*
* K2E: Clock management APIs
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_K2E_H
#define __ASM_ARCH_CLOCK_K2E_H
enum ext_clk_e {
sys_clk,
alt_core_clk,
pa_clk,
ddr3_clk,
mcm_clk,
pcie_clk,
sgmii_clk,
xgmii_clk,
usb_clk,
ext_clk_count /* number of external clocks */
};
extern unsigned int external_clk[ext_clk_count];
enum clk_e {
core_pll_clk,
pass_pll_clk,
ddr3_pll_clk,
sys_clk0_clk,
sys_clk0_1_clk,
sys_clk0_2_clk,
sys_clk0_3_clk,
sys_clk0_4_clk,
sys_clk0_6_clk,
sys_clk0_8_clk,
sys_clk0_12_clk,
sys_clk0_24_clk,
sys_clk1_clk,
sys_clk1_3_clk,
sys_clk1_4_clk,
sys_clk1_6_clk,
sys_clk1_12_clk,
sys_clk2_clk,
sys_clk3_clk
};
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
DDR3_PLL,
};
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
#endif

23
arch/arm/include/asm/arch-keystone/clock-k2hk.h
View File

@ -10,10 +10,6 @@
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
#include <asm/arch/hardware.h>
#ifndef __ASSEMBLY__
enum ext_clk_e {
sys_clk,
alt_core_clk,
@ -56,7 +52,7 @@ enum clk_e {
sys_clk3_clk
};
#define K2HK_CLK1_6 sys_clk0_6_clk
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
@ -66,15 +62,6 @@ enum pll_type_e {
DDR3A_PLL,
DDR3B_PLL,
};
#define MAIN_PLL CORE_PLL
/* PLL configuration data */
struct pll_init_data {
int pll;
int pll_m; /* PLL Multiplier */
int pll_d; /* PLL divider */
int pll_od; /* PLL output divider */
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
@ -98,12 +85,4 @@ struct pll_init_data {
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
#endif
#endif

32
arch/arm/include/asm/arch-keystone/clock.h
View File

@ -10,8 +10,40 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#ifndef __ASSEMBLY__
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/clock-k2hk.h>
#endif
#ifdef CONFIG_SOC_K2E
#include <asm/arch/clock-k2e.h>
#endif
#define MAIN_PLL CORE_PLL
#include <asm/types.h>
struct keystone_pll_regs {
u32 reg0;
u32 reg1;
};
/* PLL configuration data */
struct pll_init_data {
int pll;
int pll_m; /* PLL Multiplier */
int pll_d; /* PLL divider */
int pll_od; /* PLL output divider */
};
extern const struct keystone_pll_regs keystone_pll_regs[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
#endif
#endif

2
arch/arm/include/asm/arch-keystone/clock_defs.h
View File

@ -50,7 +50,7 @@ struct pllctl_regs {
};
static struct pllctl_regs *pllctl_regs[] = {
(struct pllctl_regs *)(CLOCK_BASE + 0x100)
(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))

56
arch/arm/include/asm/arch-keystone/ddr3.h Normal file
View File

@ -0,0 +1,56 @@
/*
* DDR3
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DDR3_H_
#define _DDR3_H_
#include <asm/arch/hardware.h>
struct ddr3_phy_config {
unsigned int pllcr;
unsigned int pgcr1_mask;
unsigned int pgcr1_val;
unsigned int ptr0;
unsigned int ptr1;
unsigned int ptr2;
unsigned int ptr3;
unsigned int ptr4;
unsigned int dcr_mask;
unsigned int dcr_val;
unsigned int dtpr0;
unsigned int dtpr1;
unsigned int dtpr2;
unsigned int mr0;
unsigned int mr1;
unsigned int mr2;
unsigned int dtcr;
unsigned int pgcr2;
unsigned int zq0cr1;
unsigned int zq1cr1;
unsigned int zq2cr1;
unsigned int pir_v1;
unsigned int pir_v2;
};
struct ddr3_emif_config {
unsigned int sdcfg;
unsigned int sdtim1;
unsigned int sdtim2;
unsigned int sdtim3;
unsigned int sdtim4;
unsigned int zqcfg;
unsigned int sdrfc;
};
void ddr3_init(void);
void ddr3_reset_ddrphy(void);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
#endif

44
arch/arm/include/asm/arch-keystone/hardware-k2e.h Normal file
View File

@ -0,0 +1,44 @@
/*
* K2E: SoC definitions
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_K2E_H
#define __ASM_ARCH_HARDWARE_K2E_H
/* PA SS Registers */
#define KS2_PASS_BASE 0x24000000
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD_RST 0
#define KS2_LPSC_USB_1 1
#define KS2_LPSC_USB 2
#define KS2_LPSC_EMIF25_SPI 3
#define KS2_LPSC_TSIP 4
#define KS2_LPSC_DEBUGSS_TRC 5
#define KS2_LPSC_TETB_TRC 6
#define KS2_LPSC_PKTPROC 7
#define KS2_LPSC_PA KS2_LPSC_PKTPROC
#define KS2_LPSC_SGMII 8
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
#define KS2_LPSC_CRYPTO 9
#define KS2_LPSC_PCIE 10
#define KS2_LPSC_VUSR0 12
#define KS2_LPSC_CHIP_SRSS 13
#define KS2_LPSC_MSMC 14
#define KS2_LPSC_EMIF4F_DDR3 23
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
/* Number of DSP cores */
#define KS2_NUM_DSPS 1
#endif

182
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
View File

@ -6,136 +6,82 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
#define K2HK_PLL_CNTRL_BASE 0x02310000
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
#define KS2_RSTCTRL_KEY 0x5a69
#define KS2_RSTCTRL_MASK 0xffff0000
#define KS2_RSTCTRL_SWRST 0xfffe0000
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
#define K2HK_PSC_BASE 0x02350000
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
#define ARM_PLL_EN BIT(13)
#define K2HK_SPI0_BASE 0x21000400
#define K2HK_SPI1_BASE 0x21000600
#define K2HK_SPI2_BASE 0x21000800
#define K2HK_SPI_BASE K2HK_SPI0_BASE
/* Chip configuration unlock codes and registers */
#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
#define KEYSTONE_KICK0_MAGIC 0x83e70b13
#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
#define KS2_PASS_BASE 0x02000000
#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
/* Power and Sleep Controller (PSC) Domains */
#define K2HK_LPSC_MOD 0
#define K2HK_LPSC_DUMMY1 1
#define K2HK_LPSC_USB 2
#define K2HK_LPSC_EMIF25_SPI 3
#define K2HK_LPSC_TSIP 4
#define K2HK_LPSC_DEBUGSS_TRC 5
#define K2HK_LPSC_TETB_TRC 6
#define K2HK_LPSC_PKTPROC 7
#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
#define K2HK_LPSC_SGMII 8
#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
#define K2HK_LPSC_CRYPTO 9
#define K2HK_LPSC_PCIE 10
#define K2HK_LPSC_SRIO 11
#define K2HK_LPSC_VUSR0 12
#define K2HK_LPSC_CHIP_SRSS 13
#define K2HK_LPSC_MSMC 14
#define K2HK_LPSC_GEM_0 15
#define K2HK_LPSC_GEM_1 16
#define K2HK_LPSC_GEM_2 17
#define K2HK_LPSC_GEM_3 18
#define K2HK_LPSC_GEM_4 19
#define K2HK_LPSC_GEM_5 20
#define K2HK_LPSC_GEM_6 21
#define K2HK_LPSC_GEM_7 22
#define K2HK_LPSC_EMIF4F_DDR3A 23
#define K2HK_LPSC_EMIF4F_DDR3B 24
#define K2HK_LPSC_TAC 25
#define K2HK_LPSC_RAC 26
#define K2HK_LPSC_RAC_1 27
#define K2HK_LPSC_FFTC_A 28
#define K2HK_LPSC_FFTC_B 29
#define K2HK_LPSC_FFTC_C 30
#define K2HK_LPSC_FFTC_D 31
#define K2HK_LPSC_FFTC_E 32
#define K2HK_LPSC_FFTC_F 33
#define K2HK_LPSC_AI2 34
#define K2HK_LPSC_TCP3D_0 35
#define K2HK_LPSC_TCP3D_1 36
#define K2HK_LPSC_TCP3D_2 37
#define K2HK_LPSC_TCP3D_3 38
#define K2HK_LPSC_VCP2X4_A 39
#define K2HK_LPSC_CP2X4_B 40
#define K2HK_LPSC_VCP2X4_C 41
#define K2HK_LPSC_VCP2X4_D 42
#define K2HK_LPSC_VCP2X4_E 43
#define K2HK_LPSC_VCP2X4_F 44
#define K2HK_LPSC_VCP2X4_G 45
#define K2HK_LPSC_VCP2X4_H 46
#define K2HK_LPSC_BCP 47
#define K2HK_LPSC_DXB 48
#define K2HK_LPSC_VUSR1 49
#define K2HK_LPSC_XGE 50
#define K2HK_LPSC_ARM_SREFLEX 51
#define K2HK_LPSC_TETRIS 52
#define KS2_LPSC_MOD 0
#define KS2_LPSC_DUMMY1 1
#define KS2_LPSC_USB 2
#define KS2_LPSC_EMIF25_SPI 3
#define KS2_LPSC_TSIP 4
#define KS2_LPSC_DEBUGSS_TRC 5
#define KS2_LPSC_TETB_TRC 6
#define KS2_LPSC_PKTPROC 7
#define KS2_LPSC_PA KS2_LPSC_PKTPROC
#define KS2_LPSC_SGMII 8
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
#define KS2_LPSC_CRYPTO 9
#define KS2_LPSC_PCIE 10
#define KS2_LPSC_SRIO 11
#define KS2_LPSC_VUSR0 12
#define KS2_LPSC_CHIP_SRSS 13
#define KS2_LPSC_MSMC 14
#define KS2_LPSC_GEM_1 16
#define KS2_LPSC_GEM_2 17
#define KS2_LPSC_GEM_3 18
#define KS2_LPSC_GEM_4 19
#define KS2_LPSC_GEM_5 20
#define KS2_LPSC_GEM_6 21
#define KS2_LPSC_GEM_7 22
#define KS2_LPSC_EMIF4F_DDR3A 23
#define KS2_LPSC_EMIF4F_DDR3B 24
#define KS2_LPSC_TAC 25
#define KS2_LPSC_RAC 26
#define KS2_LPSC_RAC_1 27
#define KS2_LPSC_FFTC_A 28
#define KS2_LPSC_FFTC_B 29
#define KS2_LPSC_FFTC_C 30
#define KS2_LPSC_FFTC_D 31
#define KS2_LPSC_FFTC_E 32
#define KS2_LPSC_FFTC_F 33
#define KS2_LPSC_AI2 34
#define KS2_LPSC_TCP3D_0 35
#define KS2_LPSC_TCP3D_1 36
#define KS2_LPSC_TCP3D_2 37
#define KS2_LPSC_TCP3D_3 38
#define KS2_LPSC_VCP2X4_A 39
#define KS2_LPSC_CP2X4_B 40
#define KS2_LPSC_VCP2X4_C 41
#define KS2_LPSC_VCP2X4_D 42
#define KS2_LPSC_VCP2X4_E 43
#define KS2_LPSC_VCP2X4_F 44
#define KS2_LPSC_VCP2X4_G 45
#define KS2_LPSC_VCP2X4_H 46
#define KS2_LPSC_BCP 47
#define KS2_LPSC_DXB 48
#define KS2_LPSC_VUSR1 49
#define KS2_LPSC_XGE 50
#define KS2_LPSC_ARM_SREFLEX 51
/* DDR3A definitions */
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
#define K2HK_DDR3A_DDRPHYC 0x02329000
/* DDR3B definitions */
#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
#define K2HK_DDR3B_DDRPHYC 0x02328000
#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
#define KS2_DDR3B_DDRPHYC 0x02328000
/* Queue manager */
#define DEVICE_QM_MANAGER_BASE 0x02a02000
#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
#define DEVICE_QM_NUM_LINKRAMS 2
#define DEVICE_QM_NUM_MEMREGIONS 20
#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
/* MSMC control */
#define K2HK_MSMC_CTRL_BASE 0x0bc00000
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
#endif /* __ASM_ARCH_HARDWARE_H */

117
arch/arm/include/asm/arch-keystone/hardware.h
View File

@ -22,42 +22,6 @@
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
struct ddr3_phy_config {
unsigned int pllcr;
unsigned int pgcr1_mask;
unsigned int pgcr1_val;
unsigned int ptr0;
unsigned int ptr1;
unsigned int ptr2;
unsigned int ptr3;
unsigned int ptr4;
unsigned int dcr_mask;
unsigned int dcr_val;
unsigned int dtpr0;
unsigned int dtpr1;
unsigned int dtpr2;
unsigned int mr0;
unsigned int mr1;
unsigned int mr2;
unsigned int dtcr;
unsigned int pgcr2;
unsigned int zq0cr1;
unsigned int zq1cr1;
unsigned int zq2cr1;
unsigned int pir_v1;
unsigned int pir_v2;
};
struct ddr3_emif_config {
unsigned int sdcfg;
unsigned int sdtim1;
unsigned int sdtim2;
unsigned int sdtim3;
unsigned int sdtim4;
unsigned int zqcfg;
unsigned int sdrfc;
};
#endif
#define BIT(x) (1 << (x))
@ -105,6 +69,11 @@ struct ddr3_emif_config {
#define NOSRA_MASK 0x08000000
#define ECC_MASK 0x00000001
/* DDR3 definitions */
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
#define KS2_DDR3A_DDRPHYC 0x02329000
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define KS2_DDR3_SDCFG_OFFSET 0x08
@ -116,39 +85,103 @@ struct ddr3_emif_config {
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
/* Boot Config */
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
/* PSC */
#define KS2_PSC_BASE 0x02350000
#define KS2_LPSC_GEM_0 15
#define KS2_LPSC_TETRIS 52
#define KS2_TETRIS_PWR_DOMAIN 31
/* Chip configuration unlock codes and registers */
#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
#define KS2_KICK0_MAGIC 0x83e70b13
#define KS2_KICK1_MAGIC 0x95a4f1e0
/* PLL control registers */
#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
#define KS2_PLL_CNTRL_BASE 0x02310000
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
#define KS2_RSTCTRL_KEY 0x5a69
#define KS2_RSTCTRL_MASK 0xffff0000
#define KS2_RSTCTRL_SWRST 0xfffe0000
/* SPI */
#define KS2_SPI0_BASE 0x21000400
#define KS2_SPI1_BASE 0x21000600
#define KS2_SPI2_BASE 0x21000800
#define KS2_SPI_BASE KS2_SPI0_BASE
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
#ifdef CONFIG_SOC_K2E
#include <asm/arch/hardware-k2e.h>
#endif
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb981) ? 1 : 0;
}
static inline int cpu_is_k2e(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb9a6) ? 1 : 0;
}
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int rev = (jtag_id >> 28) & 0xf;
return rev;
}
void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
void init_ddr3(void);
void sdelay(unsigned long);
#endif

15
arch/arm/include/asm/arch-keystone/mon.h Normal file
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@ -0,0 +1,15 @@
/*
* K2HK: secure kernel command header file
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MON_H_
#define _MON_H_
int mon_power_off(int core_id);
#endif

17
arch/arm/include/asm/arch-keystone/msmc.h Normal file
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@ -0,0 +1,17 @@
/*
* MSMC controller
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MSMC_H_
#define _MSMC_H_
#include <asm/arch/hardware.h>
void msmc_share_all_segments(int priv_id);
#endif

3
arch/arm/include/asm/arch-kirkwood/config.h
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@ -129,7 +129,8 @@
*/
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_I2C_MVTWSI
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000

1
arch/arm/include/asm/arch-omap3/cpu.h
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@ -98,7 +98,6 @@ struct ctrl_id {
#define DEBUG_BASE 0x08000000 /* debug board */
#define NAND_BASE 0x30000000 /* NAND addr */
/* (actual size small port) */
#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */

13
arch/arm/include/asm/arch-omap3/mem.h
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@ -427,20 +427,7 @@ enum {
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE FLASH_BASE
#define PISMO1_NAND_BASE NAND_BASE
#define PISMO2_CS0_BASE PISMO2_MAP1
#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
#ifndef __ASSEMBLY__

3
arch/arm/include/asm/arch-rmobile/gpio.h
View File

@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
#elif defined(CONFIG_R8A7794)
#include "r8a7794-gpio.h"
void r8a7794_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

176
arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h Normal file
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@ -0,0 +1,176 @@
#ifndef __ASM_R8A7794_H__
#define __ASM_R8A7794_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
GPIO_GP_6_24, GPIO_GP_6_25,
GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
/* IPSR7 */
GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
/* IPSR8 */
GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
/*
* From IPSR9 to IPSR10 have been removed because they does not use.
*/
/* IPSR11 */
GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
/*
* From IPSR12 to IPSR13 have been removed because they does not use.
*/
};
#endif /* __ASM_R8A7794_H__ */

14
arch/arm/include/asm/arch-rmobile/r8a7794.h Normal file
View File

@ -0,0 +1,14 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7794.h
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7794_H
#define __ASM_ARCH_R8A7794_H
#include "rcar-base.h"
#endif /* __ASM_ARCH_R8A7794_H */

4
arch/arm/include/asm/arch-rmobile/rcar-base.h
View File

@ -10,7 +10,7 @@
#define __ASM_ARCH_RCAR_BASE_H
/*
* R-Car (R8A7790/R8A7791) I/O Addresses
* R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
@ -116,7 +116,7 @@
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_TRAB_BASE 0xFF800B00
#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0

2
arch/arm/include/asm/arch-rmobile/rmobile.h
View File

@ -10,6 +10,8 @@
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#else
#error "SOC Name not defined"
#endif

2
arch/arm/include/asm/arch-sunxi/gpio.h
View File

@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
int sunxi_name_to_gpio(const char *name);
#define name_to_gpio(name) sunxi_name_to_gpio(name)
#endif /* _SUNXI_GPIO_H */

15
arch/arm/include/asm/arch-sunxi/i2c.h Normal file
View File

@ -0,0 +1,15 @@
/*
* Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_I2C_H_
#define _SUNXI_I2C_H_
#include <asm/arch/cpu.h>
#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
#define CONFIG_SYS_TCLK 24000000
#endif

5
arch/arm/include/asm/arch-sunxi/timer.h
View File

@ -11,6 +11,11 @@
#ifndef _SUNXI_TIMER_H_
#define _SUNXI_TIMER_H_
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
#ifndef __ASSEMBLY__
#include <linux/types.h>

11
arch/arm/include/asm/armv7.h
View File

@ -78,13 +78,18 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
int armv7_switch_nonsec(void);
int armv7_switch_hyp(void);
int armv7_init_nonsec(void);
int armv7_update_dt(void *fdt);
/* defined in assembly file */
unsigned int _nonsec_init(void);
void _do_nonsec_entry(void *target_pc, unsigned long r0,
unsigned long r1, unsigned long r2);
void _smp_pen(void);
void _switch_to_hyp(void);
extern char __secure_start[];
extern char __secure_end[];
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
#endif /* ! __ASSEMBLY__ */

8
arch/arm/include/asm/omap_common.h
View File

@ -595,6 +595,14 @@ static inline u32 omap_revision(void)
return *omap_si_rev;
}
#define OMAP44xx 0x44000000
static inline u8 is_omap44xx(void)
{
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFF000000) == OMAP44xx;
};
#define OMAP54xx 0x54000000
static inline u8 is_omap54xx(void)

2
arch/arm/include/asm/proc-armv/ptrace.h
View File

@ -38,12 +38,14 @@ struct pt_regs {
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
#define ABT_MODE 0x17
#define HYP_MODE 0x1a
#define UND_MODE 0x1b
#define SYSTEM_MODE 0x1f
#define MODE_MASK 0x1f
#define T_BIT 0x20
#define F_BIT 0x40
#define I_BIT 0x80
#define A_BIT 0x100
#define CC_V_BIT (1 << 28)
#define CC_C_BIT (1 << 29)
#define CC_Z_BIT (1 << 30)

35
arch/arm/include/asm/psci.h Normal file
View File

@ -0,0 +1,35 @@
/*
* Copyright (C) 2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
/* PSCI interface */
#define ARM_PSCI_FN_BASE 0x95c1ba5e
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1)
#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3)
#define ARM_PSCI_RET_SUCCESS 0
#define ARM_PSCI_RET_NI (-1)
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
#endif /* __ARM_PSCI_H__ */

26
arch/arm/include/asm/secure.h Normal file
View File

@ -0,0 +1,26 @@
#ifndef __ASM_SECURE_H
#define __ASM_SECURE_H
#include <config.h>
#ifdef CONFIG_ARMV7_SECURE_BASE
/*
* Warning, horror ahead.
*
* The target code lives in our "secure ram", but u-boot doesn't know
* that, and has blindly added reloc_off to every relocation
* entry. Gahh. Do the opposite conversion. This hack also prevents
* GCC from generating code veeners, which u-boot doesn't relocate at
* all...
*/
#define secure_ram_addr(_fn) ({ \
DECLARE_GLOBAL_DATA_PTR; \
void *__fn = _fn; \
typeof(_fn) *__tmp = (__fn - gd->reloc_off); \
__tmp; \
})
#else
#define secure_ram_addr(_fn) (_fn)
#endif
#endif

14
arch/arm/lib/bootm-fdt.c
View File

@ -17,13 +17,14 @@
#include <common.h>
#include <fdt_support.h>
#include <asm/armv7.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_fixup_memory_node(void *blob)
int arch_fixup_fdt(void *blob)
{
bd_t *bd = gd->bd;
int bank;
int bank, ret;
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
@ -32,5 +33,12 @@ int arch_fixup_memory_node(void *blob)
size[bank] = bd->bi_dram[bank].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
if (ret)
return ret;
ret = armv7_update_dt(blob);
#endif
return ret;
}

31
arch/arm/lib/bootm.c
View File

@ -20,6 +20,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/bootm.h>
#include <asm/secure.h>
#include <linux/compiler.h>
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
@ -184,27 +185,17 @@ static void setup_end_tag(bd_t *bd)
__weak void setup_board_tags(struct tag **in_params) {}
#ifdef CONFIG_ARM64
static void do_nonsec_virt_switch(void)
{
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
if (armv7_switch_nonsec() == 0)
#ifdef CONFIG_ARMV7_VIRT
if (armv7_switch_hyp() == 0)
debug("entered HYP mode\n");
#else
debug("entered non-secure state\n");
#endif
#endif
#ifdef CONFIG_ARM64
smp_kick_all_cpus();
flush_dcache_all(); /* flush cache before swtiching to EL2 */
armv8_switch_to_el2();
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
armv8_switch_to_el1();
#endif
#endif
}
#endif
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
@ -242,7 +233,6 @@ static void boot_prep_linux(bootm_headers_t *images)
printf("FDT and ATAGS support not compiled in - hanging\n");
hang();
}
do_nonsec_virt_switch();
}
/* Subcommand: GO */
@ -260,8 +250,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
if (!fake)
if (!fake) {
do_nonsec_virt_switch();
kernel_entry(images->ft_addr);
}
#else
unsigned long machid = gd->bd->bi_arch_number;
char *s;
@ -287,8 +279,15 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
else
r2 = gd->bd->bi_boot_params;
if (!fake)
if (!fake) {
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
armv7_init_nonsec();
secure_ram_addr(_do_nonsec_entry)(kernel_entry,
0, machid, r2);
#else
kernel_entry(0, machid, r2);
#endif
}
#endif
}
@ -360,7 +359,7 @@ void boot_prep_vxworks(bootm_headers_t *images)
if (images->ft_addr) {
off = fdt_path_offset(images->ft_addr, "/memory");
if (off < 0) {
if (arch_fixup_memory_node(images->ft_addr))
if (arch_fixup_fdt(images->ft_addr))
puts("## WARNING: fixup memory failed!\n");
}
}

2
arch/arm/lib/interrupts.c
View File

@ -103,7 +103,7 @@ void show_regs (struct pt_regs *regs)
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
"UK8_32", "UK9_32", "UK10_32", "UND_32",
"UK8_32", "UK9_32", "HYP_32", "UND_32",
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
};

2
arch/arm/lib/sections.c
View File

@ -25,4 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
char __secure_start[0] __attribute__((section(".__secure_start")));
char __secure_end[0] __attribute__((section(".__secure_end")));
char _end[0] __attribute__((section(".__end")));

30
board/gumstix/pepper/board.c
View File

@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
(MT47H128M16RT25E_RD_DQS<<10) |
(MT47H128M16RT25E_RD_DQS<<0)),
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
(MT47H128M16RT25E_WR_DQS<<20) |
(MT47H128M16RT25E_WR_DQS<<10) |
(MT47H128M16RT25E_WR_DQS<<0)),
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
(MT47H128M16RT25E_PHY_WRLVL<<20) |
(MT47H128M16RT25E_PHY_WRLVL<<10) |
(MT47H128M16RT25E_PHY_WRLVL<<0)),
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {

9
board/renesas/alt/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# board/renesas/alt/Makefile
#
# Copyright (C) 2014 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
obj-y := alt.o qos.o

173
board/renesas/alt/alt.c Normal file
View File

@ -0,0 +1,173 @@
/*
* board/renesas/alt/alt.c
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* QoS */
qos_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP719 (1 << 19)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
int board_early_init_f(void)
{
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* SCIF0 */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
return 0;
}
void arch_preboot_os(void)
{
/* Disable TMU0 */
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7794_pinmux_init();
/* Ether Enable */
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_RXD1, NULL);
gpio_request(GPIO_FN_ETH_LINK, NULL);
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
gpio_request(GPIO_FN_ETH_MDIO, NULL);
gpio_request(GPIO_FN_ETH_TXD1, NULL);
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
gpio_request(GPIO_FN_IRQ8, NULL);
/* PHY reset */
gpio_request(GPIO_GP_1_24, NULL);
gpio_direction_output(GPIO_GP_1_24, 0);
mdelay(20);
gpio_set_value(GPIO_GP_1_24, 1);
udelay(1);
return 0;
}
#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
int ret = -ENODEV;
u32 val;
unsigned char enetaddr[6];
ret = sh_eth_initialize(bis);
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
return ret;
/* Set Mac address */
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
enetaddr[2] << 8 | enetaddr[3];
writel(val, CXR24);
val = enetaddr[4] << 8 | enetaddr[5];
writel(val, CXR25);
return ret;
#else
return 0;
#endif
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
}
int board_late_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
u8 val;
i2c_set_bus_num(1); /* PowerIC connected to ch3 */
i2c_init(400000, 0);
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}

944
board/renesas/alt/qos.c Normal file
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@ -0,0 +1,944 @@
/*
* board/renesas/alt/qos.c
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
/* QoS version 0.10 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
DBSC3_15,
DBSC3_NR,
};
static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
};
static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
};
void qos_init(void)
{
int i;
struct rcar_s3c *s3c;
struct rcar_s3c_qos *s3c_qos;
struct rcar_dbsc3_qos *qos_addr;
struct rcar_mxi *mxi;
struct rcar_mxi_qos *mxi_qos;
struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x1F0D0B0A, &s3c->s3crorr);
writel(0x1F0D0B09, &s3c->s3cworr);
/* QoS Control Registers */
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x80928092, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20DC, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960020, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA20DC, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20FA, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960020, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA20FA, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
/* DBSC -QoS */
/* DBSC0 - Read */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x0000207D, &qos_addr->dbtmval0);
writel(0x00002053, &qos_addr->dbtmval1);
writel(0x0000202A, &qos_addr->dbtmval2);
writel(0x00001FBD, &qos_addr->dbtmval3);
writel(0x00000001, &qos_addr->dbrqctr);
writel(0x00002064, &qos_addr->dbthres0);
writel(0x0000203E, &qos_addr->dbthres1);
writel(0x00002019, &qos_addr->dbthres2);
writel(0x00000001, &qos_addr->dblgqon);
}
/* DBSC0 - Write */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x0000207D, &qos_addr->dbtmval0);
writel(0x00002053, &qos_addr->dbtmval1);
writel(0x00002043, &qos_addr->dbtmval2);
writel(0x00002030, &qos_addr->dbtmval3);
writel(0x00000001, &qos_addr->dbrqctr);
writel(0x00002064, &qos_addr->dbthres0);
writel(0x0000203E, &qos_addr->dbthres1);
writel(0x00002031, &qos_addr->dbthres2);
writel(0x00000001, &qos_addr->dblgqon);
}
/* CCI-400 -QoS */
writel(0x20001000, CCI_400_MAXOT_1);
writel(0x20001000, CCI_400_MAXOT_2);
writel(0x0000000C, CCI_400_QOSCNTL_1);
writel(0x0000000C, CCI_400_QOSCNTL_2);
/* MXI -QoS */
/* Transaction Control (MXI) */
mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
/* QoS Control (MXI) */
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000E, &mxi_qos->du0);
/* AXI -QoS */
/* Transaction Control (MXI) */
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002037, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00001FF0, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000206E, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020EB, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020EB, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020EB, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020EB, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x000020AA, &axi_qos->qosthres0);
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x000020AA, &axi_qos->qosthres0);
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00001FF0, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
writel(0x00000003, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
writel(0x00000003, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
writel(0x00000003, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
writel(0x00000003, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00000001, &axi_qos->qosthres0);
writel(0x00000001, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}

12
board/renesas/alt/qos.h Normal file
View File

@ -0,0 +1,12 @@
/*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __QOS_H__
#define __QOS_H__
void qos_init(void);
#endif

4
board/sunxi/Makefile
View File

@ -10,4 +10,8 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o

67
board/sunxi/board.c
View File

@ -12,10 +12,19 @@
*/
#include <common.h>
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
#ifdef CONFIG_AXP209_POWER
#include <axp209.h>
#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/io.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -106,15 +115,73 @@ int board_mmc_init(bd_t *bis)
}
#endif
void i2c_init_board(void)
{
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
clock_twi_onoff(0, 1);
}
#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
int power_failed = 0;
unsigned long ramsize;
#ifdef CONFIG_AXP152_POWER
power_failed = axp152_init();
power_failed |= axp152_set_dcdc2(1400);
power_failed |= axp152_set_dcdc3(1500);
power_failed |= axp152_set_dcdc4(1250);
power_failed |= axp152_set_ldo2(3000);
#endif
#ifdef CONFIG_AXP209_POWER
power_failed |= axp209_init();
power_failed |= axp209_set_dcdc2(1400);
power_failed |= axp209_set_dcdc3(1250);
power_failed |= axp209_set_ldo2(3000);
power_failed |= axp209_set_ldo3(2800);
power_failed |= axp209_set_ldo4(2800);
#endif
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);
if (!ramsize)
hang();
/*
* Only clock up the CPU to full speed if we are reasonably
* assured it's being powered with suitable core voltage
*/
if (!power_failed)
clock_set_pll1(CONFIG_CLK_FULL_SPEED);
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
#endif
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
if (!getenv("ethaddr")) {
uint32_t reg_val = readl(SUNXI_SID_BASE);
if (reg_val) {
uint8_t mac_addr[6];
mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
mac_addr[1] = (reg_val >> 0) & 0xff;
reg_val = readl(SUNXI_SID_BASE + 0x0c);
mac_addr[2] = (reg_val >> 24) & 0xff;
mac_addr[3] = (reg_val >> 16) & 0xff;
mac_addr[4] = (reg_val >> 8) & 0xff;
mac_addr[5] = (reg_val >> 0) & 0xff;
eth_setenv_enetaddr("ethaddr", mac_addr);
}
}
return 0;
}
#endif

32
board/sunxi/dram_a13_oli_micro.c Normal file
View File

@ -0,0 +1,32 @@
/* this file is generated, don't edit it yourself */
#include <common.h>
#include <asm/arch/dram.h>
static struct dram_para dram_para = {
.clock = 408,
.type = 3,
.rank_num = 1,
.density = 2048,
.io_width = 16,
.bus_width = 16,
.cas = 9,
.zq = 123,
.odt_en = 0,
.size = 256,
.tpr0 = 0x42d899b7,
.tpr1 = 0xa090,
.tpr2 = 0x22a00,
.tpr3 = 0,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = 0,
.emr2 = 0x10,
.emr3 = 0,
};
unsigned long sunxi_dram_init(void)
{
return dramc_init(&dram_para);
}

31
board/sunxi/dram_cubieboard.c Normal file
View File

@ -0,0 +1,31 @@
/* this file is generated, don't edit it yourself */
#include <common.h>
#include <asm/arch/dram.h>
static struct dram_para dram_para = {
.clock = 480,
.type = 3,
.rank_num = 1,
.density = 4096,
.io_width = 16,
.bus_width = 32,
.cas = 6,
.zq = 123,
.odt_en = 0,
.size = 1024,
.tpr0 = 0x30926692,
.tpr1 = 0x1090,
.tpr2 = 0x1a0c8,
.tpr3 = 0,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = 0,
.emr2 = 0,
.emr3 = 0,
};
unsigned long sunxi_dram_init(void)
{
return dramc_init(&dram_para);
}

31
board/sunxi/dram_cubieboard2.c Normal file
View File

@ -0,0 +1,31 @@
/* this file is generated, don't edit it yourself */
#include <common.h>
#include <asm/arch/dram.h>
static struct dram_para dram_para = {
.clock = 480,
.type = 3,
.rank_num = 1,
.density = 4096,
.io_width = 16,
.bus_width = 32,
.cas = 9,
.zq = 0x7f,
.odt_en = 0,
.size = 1024,
.tpr0 = 0x42d899b7,
.tpr1 = 0xa090,
.tpr2 = 0x22a00,
.tpr3 = 0x0,
.tpr4 = 0x1,
.tpr5 = 0x0,
.emr1 = 0x4,
.emr2 = 0x10,
.emr3 = 0x0,
};
unsigned long sunxi_dram_init(void)
{
return dramc_init(&dram_para);
}

31
board/sunxi/dram_r7dongle.c Normal file
View File

@ -0,0 +1,31 @@
/* this file is generated, don't edit it yourself */
#include <common.h>
#include <asm/arch/dram.h>
static struct dram_para dram_para = {
.clock = 384,
.type = 3,
.rank_num = 1,
.density = 2048,
.io_width = 8,
.bus_width = 32,
.cas = 9,
.zq = 123,
.odt_en = 0,
.size = 1024,
.tpr0 = 0x42d899b7,
.tpr1 = 0xa090,
.tpr2 = 0x22a00,
.tpr3 = 0,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = 0x04,
.emr2 = 0x10,
.emr3 = 0,
};
unsigned long sunxi_dram_init(void)
{
return dramc_init(&dram_para);
}

11
board/sunxi/gmac.c
View File

@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
#else
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII);
#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
#else
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
}

30
board/ti/am335x/board.c
View File

@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
(MT47H128M16RT25E_RD_DQS<<10) |
(MT47H128M16RT25E_RD_DQS<<0)),
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
(MT47H128M16RT25E_WR_DQS<<20) |
(MT47H128M16RT25E_WR_DQS<<10) |
(MT47H128M16RT25E_WR_DQS<<0)),
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
(MT47H128M16RT25E_PHY_WRLVL<<20) |
(MT47H128M16RT25E_PHY_WRLVL<<10) |
(MT47H128M16RT25E_PHY_WRLVL<<0)),
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {

14
board/ti/am43xx/board.c
View File

@ -19,6 +19,7 @@
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
#include <power/pmic.h>
#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
@ -605,6 +606,19 @@ void sdram_init(void)
}
#endif
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
power_tps65218_init(I2C_PMIC);
p = pmic_get("TPS65218_PMIC");
if (p && !pmic_probe(p))
puts("PMIC: TPS65218\n");
return 0;
}
int board_init(void)
{
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;

7
board/ti/dra7xx/evm.c
View File

@ -163,6 +163,8 @@ int spl_start_uboot(void)
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
extern u32 *const omap_si_rev;
static void cpsw_control(int enabled)
{
/* VTP can be added here */
@ -189,7 +191,7 @@ static struct cpsw_platform_data cpsw_data = {
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
@ -260,6 +262,9 @@ int board_eth_init(bd_t *bis)
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);

12
board/ti/dra7xx/mux_data.h
View File

@ -56,6 +56,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
{VIN2A_D12, (M3) },
{VIN2A_D13, (M3) },
{VIN2A_D14, (M3) },
{VIN2A_D15, (M3) },
{VIN2A_D16, (M3) },
{VIN2A_D17, (M3) },
{VIN2A_D18, (IEN | M3)},
{VIN2A_D19, (IEN | M3)},
{VIN2A_D20, (IEN | M3)},
{VIN2A_D21, (IEN | M3)},
{VIN2A_D22, (IEN | M3)},
{VIN2A_D23, (IEN | M3)},
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */

9
board/ti/k2hk_evm/Makefile
View File

@ -1,9 +0,0 @@
#
# K2HK-EVM: board Makefile
# (C) Copyright 2012-2014
# Texas Instruments Incorporated, <www.ti.com>
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
obj-y += ddr3.o

268
board/ti/k2hk_evm/ddr3.c
View File

@ -1,268 +0,0 @@
/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <i2c.h>
/************************* *****************************/
static struct ddr3_phy_config ddr3phy_1600_64A = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0D861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
.dcr_val = ((1 << 10) | (1 << 27)),
.dtpr0 = 0xA19DBB66ul,
.dtpr1 = 0x12868300ul,
.dtpr2 = 0x50035200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x730035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
static struct ddr3_emif_config ddr3_1600_64 = {
.sdcfg = 0x6200CE6aul,
.sdtim1 = 0x16709C55ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x435DFF54ul,
.sdtim4 = 0x553F0CFFul,
.zqcfg = 0xF0073200ul,
.sdrfc = 0x00001869ul,
};
static struct ddr3_phy_config ddr3phy_1600_32 = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0D861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
.dcr_val = ((1 << 10) | (1 << 27)),
.dtpr0 = 0xA19DBB66ul,
.dtpr1 = 0x12868300ul,
.dtpr2 = 0x50035200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x730035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
static struct ddr3_emif_config ddr3_1600_32 = {
.sdcfg = 0x6200DE6aul,
.sdtim1 = 0x16709C55ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x435DFF54ul,
.sdtim4 = 0x553F0CFFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};
/************************* *****************************/
static struct ddr3_phy_config ddr3phy_1333_64A = {
.pllcr = 0x0005C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0B4515C2ul,
.ptr4 = 0x0A6E08B4ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
NOSRA_MASK | UDIMM_MASK),
.dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
.dtpr0 = 0x8558AA55ul,
.dtpr1 = 0x12857280ul,
.dtpr2 = 0x5002C200ul,
.mr0 = 0x00001A60ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000010ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F065B8ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
static struct ddr3_emif_config ddr3_1333_64 = {
.sdcfg = 0x62008C62ul,
.sdtim1 = 0x125C8044ul,
.sdtim2 = 0x00001D29ul,
.sdtim3 = 0x32CDFF43ul,
.sdtim4 = 0x543F0ADFul,
.zqcfg = 0xF0073200ul,
.sdrfc = 0x00001457ul,
};
static struct ddr3_phy_config ddr3phy_1333_32 = {
.pllcr = 0x0005C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0B4515C2ul,
.ptr4 = 0x0A6E08B4ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
NOSRA_MASK | UDIMM_MASK),
.dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
.dtpr0 = 0x8558AA55ul,
.dtpr1 = 0x12857280ul,
.dtpr2 = 0x5002C200ul,
.mr0 = 0x00001A60ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000010ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F065B8ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
static struct ddr3_emif_config ddr3_1333_32 = {
.sdcfg = 0x62009C62ul,
.sdtim1 = 0x125C8044ul,
.sdtim2 = 0x00001D29ul,
.sdtim3 = 0x32CDFF43ul,
.sdtim4 = 0x543F0ADFul,
.zqcfg = 0xf0073200ul,
.sdrfc = 0x00001457ul,
};
/************************* *****************************/
static struct ddr3_phy_config ddr3phy_1333_64 = {
.pllcr = 0x0005C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0B4515C2ul,
.ptr4 = 0x0A6E08B4ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
.dcr_val = ((1 << 10) | (1 << 27)),
.dtpr0 = 0x8558AA55ul,
.dtpr1 = 0x12857280ul,
.dtpr2 = 0x5002C200ul,
.mr0 = 0x00001A60ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000010ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F065B8ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
/******************************************************/
int get_dimm_params(char *dimm_name)
{
u8 spd_params[256];
int ret;
int old_bus;
i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
old_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
ret = i2c_read(0x53, 0, 1, spd_params, 256);
i2c_set_bus_num(old_bus);
dimm_name[0] = '\0';
if (ret) {
puts("Cannot read DIMM params\n");
return 1;
}
/*
* We need to convert spd data to dimm parameters
* and to DDR3 EMIF and PHY regirsters values.
* For now we just return DIMM type string value.
* Caller may use this value to choose appropriate
* a pre-set DDR3 configuration
*/
strncpy(dimm_name, (char *)&spd_params[0x80], 18);
dimm_name[18] = '\0';
return 0;
}
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
void init_ddr3(void)
{
char dimm_name[32];
get_dimm_params(dimm_name);
printf("Detected SO-DIMM [%s]\n", dimm_name);
if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
init_pll(&ddr3a_400);
if (cpu_revision() > 0) {
init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
} else {
init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
}
} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
init_pll(&ddr3a_333);
if (cpu_revision() > 0) {
init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
} else {
init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
}
} else {
printf("Unknown SO-DIMM. Cannot configure DDR3\n");
while (1)
;
}
init_pll(&ddr3b_333);
init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
}

13
board/ti/ks2_evm/Makefile Normal file
View File

@ -0,0 +1,13 @@
#
# KS2-EVM: board Makefile
# (C) Copyright 2012-2014
# Texas Instruments Incorporated, <www.ti.com>
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
obj-y += ddr3_cfg.o
obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o

28
board/ti/k2hk_evm/README → board/ti/ks2_evm/README_K2HK
View File

@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h
Supported boot modes:
- SPI NOR boot
- AEMIF NAND boot
Supported image formats:-
- u-boot.bin: for loading and running u-boot.bin through Texas instruments
code composure studio (CCS)
- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
- u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
Build instructions:
===================
@ -55,6 +57,10 @@ To build u-boot-spi.gph
>make k2hk_evm_config
>make u-boot-spi.gph
To build u-boot-nand.gph
>make k2hk_evm_config
>make u-boot-nand.gph
Load and Run U-Boot on K2HK EVM using CCS
=========================================
@ -115,8 +121,28 @@ instructions:-
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
run burn_uboot
run burn_uboot_spi
Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "SPI Little Endian Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
AEMIF NAND Flash programming instructions
======================================
U-Boot image can be flashed to first 1024KB of the NAND flash using following
instructions:-
1. Start CCS and run U-boot as described above.
2. Suspend Target. Select Run -> Suspend from top level menu
CortexA15_1 (Free Running)"
3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
using CCS", but using address 0x87000000.
4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
5. At the U-Boot console type following to setup u-boot environment variables.
setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
run burn_uboot_nand
Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "ARM NAND Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.

158
board/ti/k2hk_evm/board.c → board/ti/ks2_evm/board.c
View File

@ -1,45 +1,22 @@
/*
* K2HK EVM : Board initialization
* Keystone : Board initialization
*
* (C) Copyright 2012-2014
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "board.h"
#include <common.h>
#include <exports.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
DECLARE_GLOBAL_DATA_PTR;
u32 device_big_endian;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 125000000,
[pa_clk] = 122880000,
[tetris_clk] = 125000000,
[ddr3a_clk] = 100000000,
[ddr3b_clk] = 100000000,
[mcm_clk] = 312500000,
[pcie_clk] = 100000000,
[sgmii_srio_clk] = 156250000,
[xgmii_clk] = 156250000,
[usb_clk] = 100000000,
[rp1_clk] = 123456789 /* TODO: cannot find
what is that */
};
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
@ -52,18 +29,11 @@ static struct aemif_config aemif_configs[] = {
.turn_around = 3,
.width = AEMIF_WIDTH_8,
},
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1228,
PASS_PLL_983,
TETRIS_PLL_1200,
};
int dram_init(void)
{
init_ddr3();
ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
@ -71,42 +41,18 @@ int dram_init(void)
return 0;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2HK_EMAC",
.rx_flow = 22,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2HK_EMAC1",
.rx_flow = 23,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2HK_EMAC2",
.rx_flow = 24,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2HK_EMAC3",
.rx_flow = 25,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
};
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
return 0;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
int get_eth_env_param(char *env_name)
{
char *env;
int res = -1;
int res = -1;
env = getenv(env_name);
if (env)
@ -117,12 +63,14 @@ int get_eth_env_param(char *env_name)
int board_eth_init(bd_t *bis)
{
int j;
int res;
char link_type_name[32];
int j;
int res;
int port_num;
char link_type_name[32];
for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
j++) {
port_num = get_num_eth_ports();
for (j = 0; j < port_num; j++) {
sprintf(link_type_name, "sgmii%d_link_type", j);
res = get_eth_env_param(link_type_name);
if (res >= 0)
@ -135,46 +83,24 @@ int board_eth_init(bd_t *bis)
}
#endif
/* Byte swap the 32-bit data if the device is BE */
int cpu_to_bus(u32 *ptr, u32 length)
{
u32 i;
if (device_big_endian)
for (i = 0; i < length; i++, ptr++)
*ptr = __swab32(*ptr);
return 0;
}
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
return 0;
}
#endif
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#define K2_DDR3_START_ADDR 0x80000000
void ft_board_setup(void *blob, bd_t *bd)
{
u64 start[2];
u64 size[2];
char name[32], *env, *endp;
int lpae, nodeoffset;
u32 ddr3a_size;
int lpae;
char *env;
char *endp;
int nbanks;
u64 size[2];
u64 start[2];
char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
env = getenv("uinitrd_fixup");
unitrd_fixup = env && simple_strtol(env, NULL, 0);
ddr3a_size = 0;
if (lpae) {
@ -191,7 +117,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* adjust memory start address for LPAE */
if (lpae) {
start[0] -= K2_DDR3_START_ADDR;
start[0] -= CONFIG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
@ -217,10 +143,11 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, start, size, nbanks);
/* Fix up the initrd */
if (lpae) {
u64 initrd_start, initrd_end;
u32 *prop1, *prop2;
if (lpae && unitrd_fixup) {
int err;
u32 *prop1, *prop2;
u64 initrd_start, initrd_end;
nodeoffset = fdt_path_offset(blob, "/chosen");
if (nodeoffset >= 0) {
prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
@ -229,11 +156,11 @@ void ft_board_setup(void *blob, bd_t *bd)
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be32_to_cpu(*prop1);
initrd_start -= K2_DDR3_START_ADDR;
initrd_start -= CONFIG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be32_to_cpu(*prop2);
initrd_end -= K2_DDR3_START_ADDR;
initrd_end -= CONFIG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
@ -267,9 +194,10 @@ void ft_board_setup(void *blob, bd_t *bd)
void ft_board_setup_ex(void *blob, bd_t *bd)
{
int lpae;
char *env;
u64 *reserve_start, size;
int lpae;
u64 size;
char *env;
u64 *reserve_start;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
@ -286,7 +214,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
*reserve_start -= K2_DDR3_START_ADDR;
*reserve_start -= CONFIG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =

19
board/ti/ks2_evm/board.h Normal file
View File

@ -0,0 +1,19 @@
/*
* K2HK EVM : Board common header
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _KS2_BOARD
#define _KS2_BOARD
#include <asm/arch/emac_defs.h>
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
#endif

39
board/ti/ks2_evm/board_k2e.c Normal file
View File

@ -0,0 +1,39 @@
/*
* K2E EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 100000000,
[alt_core_clk] = 100000000,
[pa_clk] = 100000000,
[ddr3_clk] = 100000000,
[mcm_clk] = 312500000,
[pcie_clk] = 100000000,
[sgmii_clk] = 156250000,
[xgmii_clk] = 156250000,
[usb_clk] = 100000000,
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1200,
PASS_PLL_1000,
};
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
return 0;
}
#endif

81
board/ti/ks2_evm/board_k2hk.c Normal file
View File

@ -0,0 +1,81 @@
/*
* K2HK EVM : Board initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emac_defs.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 125000000,
[pa_clk] = 122880000,
[tetris_clk] = 125000000,
[ddr3a_clk] = 100000000,
[ddr3b_clk] = 100000000,
[mcm_clk] = 312500000,
[pcie_clk] = 100000000,
[sgmii_srio_clk] = 156250000,
[xgmii_clk] = 156250000,
[usb_clk] = 100000000,
[rp1_clk] = 123456789
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1228,
PASS_PLL_983,
TETRIS_PLL_1200,
};
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2HK_EMAC",
.rx_flow = 22,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2HK_EMAC1",
.rx_flow = 23,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2HK_EMAC2",
.rx_flow = 24,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2HK_EMAC3",
.rx_flow = 25,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
return 0;
}
#endif

170
board/ti/ks2_evm/ddr3_cfg.c Normal file
View File

@ -0,0 +1,170 @@
/*
* Keystone2: DDR3 configuration
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* DDR3 PHY configuration data with 1600M rate, 8GB size */
struct ddr3_phy_config ddr3phy_1600_8g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0D861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0xA19DBB66ul,
.dtpr1 = 0x32868300ul,
.dtpr2 = 0x50035200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x730035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
struct ddr3_emif_config ddr3_1600_8g = {
.sdcfg = 0x6200CE6Aul,
.sdtim1 = 0x16709C55ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x435DFF54ul,
.sdtim4 = 0x553F0CFFul,
.zqcfg = 0xF0073200ul,
.sdrfc = 0x00001869ul,
};
#ifdef CONFIG_K2HK_EVM
/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
struct ddr3_phy_config ddr3phy_1333_2g = {
.pllcr = 0x0005C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0B4515C2ul,
.ptr4 = 0x0A6E08B4ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x8558AA55ul,
.dtpr1 = 0x32857280ul,
.dtpr2 = 0x5002C200ul,
.mr0 = 0x00001A60ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000010ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F065B8ul,
.zq0cr1 = 0x0000005Dul,
.zq1cr1 = 0x0000005Bul,
.zq2cr1 = 0x0000005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
struct ddr3_emif_config ddr3_1333_2g = {
.sdcfg = 0x62008C62ul,
.sdtim1 = 0x125C8044ul,
.sdtim2 = 0x00001D29ul,
.sdtim3 = 0x32CDFF43ul,
.sdtim4 = 0x543F0ADFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001457ul,
};
#endif
#ifdef CONFIG_K2E_EVM
/* DDR3 PHY configuration data with 1600M rate, and 4GB size */
struct ddr3_phy_config ddr3phy_1600_4g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x08861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x9D9CBB66ul,
.dtpr1 = 0x12840300ul,
.dtpr2 = 0x5002D200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */
struct ddr3_emif_config ddr3_1600_4g = {
.sdcfg = 0x6200CE62ul,
.sdtim1 = 0x166C9855ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x421DFF53ul,
.sdtim4 = 0x543F07FFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};
#endif
int ddr3_get_dimm_params(char *dimm_name)
{
int ret;
int old_bus;
u8 spd_params[256];
i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
old_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
ret = i2c_read(0x53, 0, 1, spd_params, 256);
i2c_set_bus_num(old_bus);
dimm_name[0] = '\0';
if (ret) {
puts("Cannot read DIMM params\n");
return 1;
}
/*
* We need to convert spd data to dimm parameters
* and to DDR3 EMIF and PHY regirsters values.
* For now we just return DIMM type string value.
* Caller may use this value to choose appropriate
* a pre-set DDR3 configuration
*/
strncpy(dimm_name, (char *)&spd_params[0x80], 18);
dimm_name[18] = '\0';
return 0;
}

24
board/ti/ks2_evm/ddr3_cfg.h Normal file
View File

@ -0,0 +1,24 @@
/*
* Keystone2: DDR3 configuration
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR3_CFG_H
#define __DDR3_CFG_H
extern struct ddr3_phy_config ddr3phy_1600_8g;
extern struct ddr3_emif_config ddr3_1600_8g;
extern struct ddr3_phy_config ddr3phy_1333_2g;
extern struct ddr3_emif_config ddr3_1333_2g;
extern struct ddr3_phy_config ddr3phy_1600_4g;
extern struct ddr3_emif_config ddr3_1600_4g;
int ddr3_get_dimm_params(char *dimm_name);
#endif /* __DDR3_CFG_H */

55
board/ti/ks2_evm/ddr3_k2e.c Normal file
View File

@ -0,0 +1,55 @@
/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static int ddr3_size;
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
void ddr3_init(void)
{
char dimm_name[32];
if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
init_pll(&ddr3_400);
ddr3_get_dimm_params(dimm_name);
printf("Detected SO-DIMM [%s]\n", dimm_name);
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
/* 8G SO-DIMM */
ddr3_size = 8;
printf("DRAM: 8 GiB\n");
ddr3phy_1600_8g.zq0cr1 |= 0x10000;
ddr3phy_1600_8g.zq1cr1 |= 0x10000;
ddr3phy_1600_8g.zq2cr1 |= 0x10000;
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
/* 4G SO-DIMM */
ddr3_size = 4;
printf("DRAM: 4 GiB\n");
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
}
}
/**
* ddr3_get_size - return ddr3 size in GiB
*/
int ddr3_get_size(void)
{
return ddr3_size;
}

84
board/ti/ks2_evm/ddr3_k2hk.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
void ddr3_init(void)
{
char dimm_name[32];
ddr3_get_dimm_params(dimm_name);
printf("Detected SO-DIMM [%s]\n", dimm_name);
if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
init_pll(&ddr3a_400);
if (cpu_revision() > 0) {
if (cpu_revision() > 1) {
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
ddr3phy_1600_8g.zq0cr1 |= 0x10000;
ddr3phy_1600_8g.zq1cr1 |= 0x10000;
ddr3phy_1600_8g.zq2cr1 |= 0x10000;
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1600_8g);
} else {
/* PG 1.1 */
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1600_8g);
}
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
ddr3_1600_8g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
}
} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
init_pll(&ddr3a_333);
if (cpu_revision() > 0) {
if (cpu_revision() > 1) {
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
ddr3phy_1333_2g.zq0cr1 |= 0x10000;
ddr3phy_1333_2g.zq1cr1 |= 0x10000;
ddr3phy_1333_2g.zq2cr1 |= 0x10000;
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1333_2g);
} else {
/* PG 1.1 */
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1333_2g);
}
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
ddr3_1333_2g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
}
} else {
printf("Unknown SO-DIMM. Cannot configure DDR3\n");
while (1)
;
}
}

3
board/xilinx/zynq/Makefile
View File

@ -10,3 +10,6 @@ obj-y := board.o
# Please copy ps7_init.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
$(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes

13
boards.cfg
View File

@ -300,7 +300,8 @@ Active arm armv7 exynos samsung trats
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org>
Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 keystone ti ks2_evm k2e_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
@ -372,13 +373,19 @@ Active arm armv7 omap5 ti dra7xx
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas alt alt - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga <r.baldyga@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII -
Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede <hdegoede@redhat.com>
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>

9
common/image-fdt.c
View File

@ -450,7 +450,7 @@ __weak int ft_verify_fdt(void *fdt)
return 1;
}
__weak int arch_fixup_memory_node(void *blob)
__weak int arch_fixup_fdt(void *blob)
{
return 0;
}
@ -467,7 +467,10 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
puts(" - must RESET the board to recover.\n");
return -1;
}
arch_fixup_memory_node(blob);
if (arch_fixup_fdt(blob) < 0) {
puts("ERROR: arch specific fdt fixup failed");
return -1;
}
if (IMAGE_OF_BOARD_SETUP)
ft_board_setup(blob, gd->bd);
fdt_fixup_ethernet(blob);
@ -492,7 +495,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
if (!ft_verify_fdt(blob))
return -1;
#ifdef CONFIG_SOC_K2HK
#if defined(CONFIG_SOC_KEYSTONE)
if (IMAGE_OF_BOARD_SETUP)
ft_board_setup_ex(blob, gd->bd);
#endif

12
doc/README.nand
View File

@ -89,6 +89,10 @@ Commands:
Configuration Options:
CONFIG_SYS_NAND_U_BOOT_OFFS
NAND Offset from where SPL will read u-boot image. This is the starting
address of u-boot MTD partition in NAND.
CONFIG_CMD_NAND
Enables NAND support and commmands.
@ -226,6 +230,14 @@ Platform specific options
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
CONFIG_SPL_NAND_AM33XX_BCH
Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
hardware ECC correction. This is useful for platforms which have ELM
hardware engine and use NAND boot mode.
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
SPL-NAND driver with software ECC correction support.
CONFIG_NAND_OMAP_ECCSCHEME
On OMAP platforms, this CONFIG specifies NAND ECC scheme.
It can take following values:

1
drivers/gpio/Makefile
View File

@ -36,3 +36,4 @@ obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o

102
drivers/gpio/sunxi_gpio.c Normal file
View File

@ -0,0 +1,102 @@
/*
* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
*
* Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
*
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
static int sunxi_gpio_output(u32 pin, u32 val)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
dat = readl(&pio->dat);
if (val)
dat |= 0x1 << num;
else
dat &= ~(0x1 << num);
writel(dat, &pio->dat);
return 0;
}
static int sunxi_gpio_input(u32 pin)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
dat = readl(&pio->dat);
dat >>= num;
return dat & 0x1;
}
int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
int gpio_free(unsigned gpio)
{
return 0;
}
int gpio_direction_input(unsigned gpio)
{
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
return sunxi_gpio_input(gpio);
}
int gpio_direction_output(unsigned gpio, int value)
{
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
return sunxi_gpio_output(gpio, value);
}
int gpio_get_value(unsigned gpio)
{
return sunxi_gpio_input(gpio);
}
int gpio_set_value(unsigned gpio, int value)
{
return sunxi_gpio_output(gpio, value);
}
int sunxi_name_to_gpio(const char *name)
{
int group = 0;
int groupsize = 9 * 32;
long pin;
char *eptr;
if (*name == 'P' || *name == 'p')
name++;
if (*name >= 'A') {
group = *name - (*name > 'a' ? 'a' : 'A');
groupsize = 32;
name++;
}
pin = simple_strtol(name, &eptr, 10);
if (!*name || *eptr)
return -1;
if (pin < 0 || pin > groupsize || group >= 9)
return -1;
return group * 32 + pin;
}

2
drivers/i2c/Makefile
View File

@ -7,7 +7,6 @@
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
@ -20,6 +19,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o

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