spi: Zap CONFIG_HARD_SPI
In legacy CONFIG_HARD_SPI initalizing spi_init code, which was removed during dm conversion cleanup. So remove the dead instances of CONFIG_HARD_SPI, and related code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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8
README
8
README
@ -1932,14 +1932,6 @@ The following options need to be configured:
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SPI configuration items (port pins to use, etc). For
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an example, see include/configs/sacsng.h.
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CONFIG_HARD_SPI
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Enables a hardware SPI driver for general-purpose reads
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and writes. As with CONFIG_SOFT_SPI, the board configuration
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must define a list of chip-select function pointers.
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Currently supported on some MPC8xxx processors. For an
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example, see include/configs/mpc8349emds.h.
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CONFIG_SYS_SPI_MXC_WAIT
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Timeout for waiting until spi transfer completed.
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default: (CONFIG_SYS_HZ/100) /* 10 ms */
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@ -18,13 +18,6 @@
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#define HWCONFIG_BUFFER_SIZE 256
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#endif
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/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
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#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
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# ifndef CONFIG_HARD_SPI
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# define CONFIG_HARD_SPI
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# endif
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#endif
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#define CONFIG_LMB
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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@ -273,7 +273,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
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iopd->dat |= SPI_CS_MASK;
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}
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#endif /* CONFIG_HARD_SPI */
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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@ -208,4 +208,4 @@ void spi_cs_deactivate(struct spi_slave *slave)
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/* deactivate the spi_cs */
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setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
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}
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#endif /* CONFIG_HARD_SPI */
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#endif
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@ -257,15 +257,6 @@ __weak int init_func_vid(void)
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}
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#endif
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#if defined(CONFIG_HARD_SPI)
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static int init_func_spi(void)
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{
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puts("SPI: ");
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puts("ready\n");
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return 0;
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}
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#endif
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static int setup_mon_len(void)
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{
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#if defined(__ARM__) || defined(__MICROBLAZE__)
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@ -863,9 +854,6 @@ static const init_fnc_t init_sequence_f[] = {
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#endif
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#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
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init_func_vid,
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#endif
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#if defined(CONFIG_HARD_SPI)
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init_func_spi,
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#endif
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announce_dram_init,
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dram_init, /* configure available RAM banks */
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@ -102,7 +102,6 @@
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_HARD_SPI
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#ifdef CONFIG_CMD_SPI
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# define CONFIG_SYS_DSPI_CS2
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@ -151,7 +151,6 @@
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#ifdef CONFIG_CMD_SPI
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@ -116,7 +116,6 @@
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#ifdef CONFIG_CMD_SPI
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@ -142,7 +142,6 @@
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_HARD_SPI
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#define CONFIG_SYS_SBFHDR_SIZE 0x13
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#ifdef CONFIG_CMD_SPI
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@ -370,11 +370,6 @@
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#if defined(CONFIG_SPI_FLASH)
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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@ -386,12 +386,6 @@
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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@ -287,11 +287,6 @@
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#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
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#define CONFIG_SYS_I2C_IDT6V49205B 0x69
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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@ -182,10 +182,6 @@
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#ifndef CONFIG_TRAILBLAZER
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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@ -35,7 +35,6 @@
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#endif
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#ifdef CONFIG_CMD_SF
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#define CONFIG_HARD_SPI 1
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
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@ -38,7 +38,6 @@
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#endif
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#ifdef CONFIG_CMD_SF
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#define CONFIG_HARD_SPI 1
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
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@ -159,7 +159,6 @@
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*/
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_HARD_SPI
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/*
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* NOR FLASH setup
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@ -273,15 +272,6 @@
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* SPI setup
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*/
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#ifdef CONFIG_HARD_SPI
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#define CONFIG_SYS_GPIO1_PRELIM
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#define CONFIG_SYS_GPIO1_DIR 0x00000001
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#define CONFIG_SYS_GPIO1_DAT 0x00000001
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#endif
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/*
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* Ethernet setup
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*/
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@ -43,7 +43,6 @@
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_HARD_SPI
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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@ -143,7 +143,6 @@
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/* SPI */
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#ifdef CONFIG_CMD_SPI
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#define CONFIG_HARD_SPI
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#define CONFIG_SPI_HALF_DUPLEX
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#endif
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@ -576,11 +576,6 @@
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#if defined(CONFIG_SPI_FLASH)
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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@ -214,11 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_HARD_SPI
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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@ -66,7 +66,6 @@
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#define CONFIG_CF_DSPI
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 1
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@ -42,11 +42,6 @@
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/*
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* SPI Configs
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* */
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#define CONFIG_HARD_SPI /* puts SPI: ready */
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/*
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* MMC Configs
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* */
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@ -750,7 +750,6 @@ CONFIG_G_DNL_UMS_PRODUCT_NUM
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CONFIG_G_DNL_UMS_VENDOR_NUM
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CONFIG_H264_FREQ
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CONFIG_H8300
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CONFIG_HARD_SPI
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CONFIG_HAS_ETH0
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CONFIG_HAS_ETH1
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CONFIG_HAS_ETH2
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