Initial revision
This commit is contained in:
wdenk
parent
5d3207da3a
commit
354bc6feac
266
board/c2mon/c2mon.c
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266
board/c2mon/c2mon.c
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@ -0,0 +1,266 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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unsigned char *s = getenv ("serial#");
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puts ("Board: TTTech C2MON ");
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for (; s && *s; ++s) {
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if (*s == ' ')
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break;
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putc (*s);
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long reg;
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long int size8, size9;
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long int size = 0;
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upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 2 the SDRAM bank 2 at physical address 0.
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL,
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(ulong *)SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL,
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(ulong *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if (size < 0x02000000) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping
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*/
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br3 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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udelay (10000);
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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285
board/cogent/mb.c
Normal file
285
board/cogent/mb.c
Normal file
@ -0,0 +1,285 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <board/cogent/dipsw.h>
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#include <board/cogent/lcd.h>
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#include <board/cogent/rtc.h>
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#include <board/cogent/par.h>
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#include <board/cogent/pci.h>
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_8260)
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#include <ioports.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 0, 0, 0, 0, 0 },
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/* PA30 */ { 0, 0, 0, 0, 0, 0 },
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/* PA29 */ { 0, 0, 0, 0, 0, 0 },
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/* PA28 */ { 0, 0, 0, 0, 0, 0 },
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/* PA27 */ { 0, 0, 0, 0, 0, 0 },
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/* PA26 */ { 0, 0, 0, 0, 0, 0 },
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/* PA25 */ { 0, 0, 0, 0, 0, 0 },
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/* PA24 */ { 0, 0, 0, 0, 0, 0 },
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/* PA23 */ { 0, 0, 0, 0, 0, 0 },
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/* PA22 */ { 0, 0, 0, 0, 0, 0 },
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/* PA21 */ { 0, 0, 0, 0, 0, 0 },
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/* PA20 */ { 0, 0, 0, 0, 0, 0 },
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/* PA19 */ { 0, 0, 0, 0, 0, 0 },
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/* PA18 */ { 0, 0, 0, 0, 0, 0 },
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/* PA17 */ { 0, 0, 0, 0, 0, 0 },
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/* PA16 */ { 0, 0, 0, 0, 0, 0 },
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/* PA15 */ { 0, 0, 0, 0, 0, 0 },
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/* PA14 */ { 0, 0, 0, 0, 0, 0 },
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/* PA13 */ { 0, 0, 0, 0, 0, 0 },
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/* PA12 */ { 0, 0, 0, 0, 0, 0 },
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/* PA11 */ { 0, 0, 0, 0, 0, 0 },
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/* PA10 */ { 0, 0, 0, 0, 0, 0 },
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/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 },
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/* PA6 */ { 0, 0, 0, 0, 0, 0 },
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/* PA5 */ { 0, 0, 0, 0, 0, 0 },
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/* PA4 */ { 0, 0, 0, 0, 0, 0 },
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/* PA3 */ { 0, 0, 0, 0, 0, 0 },
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/* PA2 */ { 0, 0, 0, 0, 0, 0 },
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/* PA1 */ { 0, 0, 0, 0, 0, 0 },
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/* PA0 */ { 0, 0, 0, 0, 0, 0 }
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},
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 0, 0, 0, 0, 0, 0 },
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/* PB30 */ { 0, 0, 0, 0, 0, 0 },
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/* PB29 */ { 0, 0, 0, 0, 0, 0 },
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/* PB28 */ { 0, 0, 0, 0, 0, 0 },
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/* PB27 */ { 0, 0, 0, 0, 0, 0 },
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/* PB26 */ { 0, 0, 0, 0, 0, 0 },
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/* PB25 */ { 0, 0, 0, 0, 0, 0 },
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/* PB24 */ { 0, 0, 0, 0, 0, 0 },
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/* PB23 */ { 0, 0, 0, 0, 0, 0 },
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/* PB22 */ { 0, 0, 0, 0, 0, 0 },
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/* PB21 */ { 0, 0, 0, 0, 0, 0 },
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/* PB20 */ { 0, 0, 0, 0, 0, 0 },
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/* PB19 */ { 0, 0, 0, 0, 0, 0 },
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/* PB18 */ { 0, 0, 0, 0, 0, 0 },
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/* PB17 */ { 0, 0, 0, 0, 0, 0 },
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/* PB16 */ { 0, 0, 0, 0, 0, 0 },
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/* PB15 */ { 0, 0, 0, 0, 0, 0 },
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/* PB14 */ { 0, 0, 0, 0, 0, 0 },
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/* PB13 */ { 0, 0, 0, 0, 0, 0 },
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/* PB12 */ { 0, 0, 0, 0, 0, 0 },
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/* PB11 */ { 0, 0, 0, 0, 0, 0 },
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/* PB10 */ { 0, 0, 0, 0, 0, 0 },
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/* PB9 */ { 0, 0, 0, 0, 0, 0 },
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/* PB8 */ { 0, 0, 0, 0, 0, 0 },
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/* PB7 */ { 0, 0, 0, 0, 0, 0 },
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/* PB6 */ { 0, 0, 0, 0, 0, 0 },
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/* PB5 */ { 0, 0, 0, 0, 0, 0 },
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/* PB4 */ { 0, 0, 0, 0, 0, 0 },
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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||||
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 },
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/* PC30 */ { 0, 0, 0, 0, 0, 0 },
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/* PC29 */ { 0, 0, 0, 0, 0, 0 },
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||||
/* PC28 */ { 0, 0, 0, 0, 0, 0 },
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/* PC27 */ { 0, 0, 0, 0, 0, 0 },
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/* PC26 */ { 0, 0, 0, 0, 0, 0 },
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||||
/* PC25 */ { 0, 0, 0, 0, 0, 0 },
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/* PC24 */ { 0, 0, 0, 0, 0, 0 },
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/* PC23 */ { 0, 0, 0, 0, 0, 0 },
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/* PC22 */ { 0, 0, 0, 0, 0, 0 },
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/* PC21 */ { 0, 0, 0, 0, 0, 0 },
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/* PC20 */ { 0, 0, 0, 0, 0, 0 },
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/* PC19 */ { 0, 0, 0, 0, 0, 0 },
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/* PC18 */ { 0, 0, 0, 0, 0, 0 },
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/* PC17 */ { 0, 0, 0, 0, 0, 0 },
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/* PC16 */ { 0, 0, 0, 0, 0, 0 },
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/* PC15 */ { 0, 0, 0, 0, 0, 0 },
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/* PC14 */ { 0, 0, 0, 0, 0, 0 },
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/* PC13 */ { 0, 0, 0, 0, 0, 0 },
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/* PC12 */ { 0, 0, 0, 0, 0, 0 },
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/* PC11 */ { 0, 0, 0, 0, 0, 0 },
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/* PC10 */ { 0, 0, 0, 0, 0, 0 },
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/* PC9 */ { 0, 0, 0, 0, 0, 0 },
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/* PC8 */ { 0, 0, 0, 0, 0, 0 },
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/* PC7 */ { 0, 0, 0, 0, 0, 0 },
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/* PC6 */ { 0, 0, 0, 0, 0, 0 },
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/* PC5 */ { 0, 0, 0, 0, 0, 0 },
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/* PC4 */ { 0, 0, 0, 0, 0, 0 },
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/* PC3 */ { 0, 0, 0, 0, 0, 0 },
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/* PC2 */ { 0, 0, 0, 0, 0, 0 },
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/* PC1 */ { 0, 0, 0, 0, 0, 0 },
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }
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},
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||||
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 0, 0, 0, 0, 0, 0 },
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/* PD30 */ { 0, 0, 0, 0, 0, 0 },
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/* PD29 */ { 0, 0, 0, 0, 0, 0 },
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/* PD28 */ { 0, 0, 0, 0, 0, 0 },
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/* PD27 */ { 0, 0, 0, 0, 0, 0 },
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||||
/* PD26 */ { 0, 0, 0, 0, 0, 0 },
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||||
/* PD25 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD24 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD23 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD22 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD21 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD20 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD19 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD18 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD17 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD16 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD6 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD5 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD4 */ { 0, 0, 0, 0, 0, 0 },
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* CONFIG_8260 */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int
|
||||
checkboard(void)
|
||||
{
|
||||
puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
|
||||
COGENT_CPU_MODULE " CPU Module\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations while still
|
||||
* running in flash
|
||||
*/
|
||||
|
||||
int misc_init_f (void)
|
||||
{
|
||||
printf ("DIPSW: ");
|
||||
dipsw_init();
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
long int
|
||||
initdram(int board_type)
|
||||
{
|
||||
#if CONFIG_CMA111
|
||||
return (32L * 1024L * 1024L);
|
||||
#else
|
||||
unsigned char dipsw_val;
|
||||
int dual, size0, size1;
|
||||
long int memsize;
|
||||
|
||||
dipsw_val = dipsw_cooked();
|
||||
|
||||
dual = dipsw_val & 0x01;
|
||||
size0 = (dipsw_val & 0x08) >> 3;
|
||||
size1 = (dipsw_val & 0x04) >> 2;
|
||||
|
||||
if (size0)
|
||||
if (size1)
|
||||
memsize = 16L * 1024L * 1024L;
|
||||
else
|
||||
memsize = 1L * 1024L * 1024L;
|
||||
else
|
||||
if (size1)
|
||||
memsize = 4L * 1024L * 1024L;
|
||||
else {
|
||||
printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
|
||||
memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
|
||||
}
|
||||
|
||||
if (dual)
|
||||
memsize *= 2L;
|
||||
|
||||
return (memsize);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations after monitor
|
||||
* has been relocated into ram
|
||||
*/
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
printf ("LCD: ");
|
||||
lcd_init();
|
||||
|
||||
#if 0
|
||||
printf ("RTC: ");
|
||||
rtc_init();
|
||||
|
||||
printf ("PAR: ");
|
||||
par_init();
|
||||
|
||||
printf ("KBM: ");
|
||||
kbm_init();
|
||||
|
||||
printf ("PCI: ");
|
||||
pci_init();
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user