Convert CONFIG_EMIF4 et al to Kconfig
This converts the following to Kconfig: CONFIG_EMIF4 CONFIG_SDRC Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefano Babic <sbabic@denx.de>
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@ -150,6 +150,21 @@ config TARGET_SNIPER
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endchoice
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choice
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prompt "Memory Controller"
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default SDRC
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config SDRC
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bool "SDRC controller"
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help
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The default memory controller on most OMAP3 boards is SDRC.
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config EMIF4
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bool "EMIF4 controller"
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help
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Enable this on boards like AM3517 which use EMIF4 controller
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endchoice
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config SPL_OMAP3_ID_NAND
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bool "Support OMAP3-specific ID and MFR function"
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help
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@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80100000
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# CONFIG_SPL_GPIO_SUPPORT is not set
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CONFIG_TARGET_AM3517_CRANE=y
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CONFIG_EMIF4=y
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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# CONFIG_SPL_EXT_SUPPORT is not set
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@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x80100000
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CONFIG_TI_COMMON_CMD_OPTIONS=y
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# CONFIG_SPL_GPIO_SUPPORT is not set
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CONFIG_TARGET_AM3517_EVM=y
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CONFIG_EMIF4=y
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CONFIG_BOOTDELAY=10
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CONFIG_VERSION_VARIABLE=y
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CONFIG_SPL=y
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@ -3,6 +3,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80008000
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CONFIG_TARGET_CM_T3517=y
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CONFIG_EMIF4=y
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CONFIG_BOOTDELAY=3
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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@ -3,6 +3,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80008000
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CONFIG_TARGET_ECO5PK=y
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CONFIG_EMIF4=y
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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# CONFIG_SPL_EXT_SUPPORT is not set
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@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80008000
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# CONFIG_SPL_GPIO_SUPPORT is not set
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CONFIG_TARGET_MCX=y
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CONFIG_EMIF4=y
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CONFIG_VIDEO=y
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CONFIG_BOOTDELAY=3
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# CONFIG_CONSOLE_MUX is not set
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@ -3,6 +3,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80008000
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CONFIG_TARGET_MT_VENTOUX=y
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CONFIG_EMIF4=y
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CONFIG_VIDEO=y
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CONFIG_BOOTDELAY=10
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# CONFIG_CONSOLE_MUX is not set
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@ -3,6 +3,7 @@ CONFIG_ARM=y
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CONFIG_ARCH_OMAP2PLUS=y
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CONFIG_SYS_TEXT_BASE=0x80008000
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CONFIG_TARGET_TWISTER=y
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CONFIG_EMIF4=y
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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# CONFIG_SPL_EXT_SUPPORT is not set
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@ -16,7 +16,6 @@
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -14,7 +14,6 @@
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#define __CONFIG_H
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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@ -24,8 +24,6 @@
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*/
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#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -23,8 +23,6 @@
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* to be on the safe side once the default is changed.
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*/
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -15,8 +15,6 @@
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#define CONFIG_MACH_TYPE MACH_TYPE_MCX
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -33,8 +33,6 @@
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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#include <asm/arch/mem.h>
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@ -39,7 +39,6 @@
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* DRAM
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*/
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#define CONFIG_SDRC
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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@ -16,8 +16,6 @@
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -17,8 +17,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_SDRC /* Has an SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -21,9 +21,6 @@
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap.h>
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/* The chip has SDRC controller */
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#define CONFIG_SDRC
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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@ -25,8 +25,6 @@
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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@ -562,7 +562,6 @@ CONFIG_EHCI_MMIO_BIG_ENDIAN
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CONFIG_EHCI_MXS_PORT0
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CONFIG_EHCI_MXS_PORT1
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CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
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CONFIG_EMIF4
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CONFIG_EMMC_BOOT
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CONFIG_EMU
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CONFIG_ENABLE_36BIT_PHYS
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@ -1973,7 +1972,6 @@ CONFIG_SCSI_DEV_LIST
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CONFIG_SC_TIMER_CLK
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CONFIG_SDCARD
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CONFIG_SDRAM_OFFSET_FOR_RT
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CONFIG_SDRC
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CONFIG_SD_BOOT_QSPI
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CONFIG_SECBOOT
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CONFIG_SECURE_BL1_ONLY
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