From 3374d28b3443cc5565816d1f58d01ebfa14ea5ae Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 14 Nov 2019 12:57:38 -0700 Subject: [PATCH] common: Drop checkicache() and checkdcache() These are used by only one arch and only within a single file. Drop the declarations from the common file. Signed-off-by: Simon Glass Reviewed-by: Tom Rini --- arch/powerpc/cpu/mpc8xx/cpu.c | 152 +++++++++++++++++----------------- include/common.h | 2 - 2 files changed, 76 insertions(+), 78 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 2b7c5d4301..0604433e72 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -35,6 +35,82 @@ DECLARE_GLOBAL_DATA_PTR; +/* ------------------------------------------------------------------------- */ +/* L1 i-cache */ + +int checkicache(void) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + memctl8xx_t __iomem *memctl = &immap->im_memctl; + u32 cacheon = rd_ic_cst() & IDC_ENABLED; + /* probe in flash memoryarea */ + u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; + u32 m; + u32 lines = -1; + + wr_ic_cst(IDC_UNALL); + wr_ic_cst(IDC_INVALL); + wr_ic_cst(IDC_DISABLE); + __asm__ volatile ("isync"); + + while (!((m = rd_ic_cst()) & IDC_CERR2)) { + wr_ic_adr(k); + wr_ic_cst(IDC_LDLCK); + __asm__ volatile ("isync"); + + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_ic_cst(IDC_UNALL); + wr_ic_cst(IDC_INVALL); + + if (cacheon) + wr_ic_cst(IDC_ENABLE); + else + wr_ic_cst(IDC_DISABLE); + + __asm__ volatile ("isync"); + + return lines << 4; +}; + +/* ------------------------------------------------------------------------- */ +/* L1 d-cache */ +/* call with cache disabled */ + +static int checkdcache(void) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + memctl8xx_t __iomem *memctl = &immap->im_memctl; + u32 cacheon = rd_dc_cst() & IDC_ENABLED; + /* probe in flash memoryarea */ + u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; + u32 m; + u32 lines = -1; + + wr_dc_cst(IDC_UNALL); + wr_dc_cst(IDC_INVALL); + wr_dc_cst(IDC_DISABLE); + + while (!((m = rd_dc_cst()) & IDC_CERR2)) { + wr_dc_adr(k); + wr_dc_cst(IDC_LDLCK); + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_dc_cst(IDC_UNALL); + wr_dc_cst(IDC_INVALL); + + if (cacheon) + wr_dc_cst(IDC_ENABLE); + else + wr_dc_cst(IDC_DISABLE); + + return lines << 4; +}; + static int check_CPU(long clock, uint pvr, uint immr) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; @@ -99,82 +175,6 @@ int checkcpu(void) return check_CPU(clock, pvr, immr); } -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ - -int checkicache(void) -{ - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - memctl8xx_t __iomem *memctl = &immap->im_memctl; - u32 cacheon = rd_ic_cst() & IDC_ENABLED; - /* probe in flash memoryarea */ - u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; - u32 m; - u32 lines = -1; - - wr_ic_cst(IDC_UNALL); - wr_ic_cst(IDC_INVALL); - wr_ic_cst(IDC_DISABLE); - __asm__ volatile ("isync"); - - while (!((m = rd_ic_cst()) & IDC_CERR2)) { - wr_ic_adr(k); - wr_ic_cst(IDC_LDLCK); - __asm__ volatile ("isync"); - - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_ic_cst(IDC_UNALL); - wr_ic_cst(IDC_INVALL); - - if (cacheon) - wr_ic_cst(IDC_ENABLE); - else - wr_ic_cst(IDC_DISABLE); - - __asm__ volatile ("isync"); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ -/* call with cache disabled */ - -int checkdcache(void) -{ - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - memctl8xx_t __iomem *memctl = &immap->im_memctl; - u32 cacheon = rd_dc_cst() & IDC_ENABLED; - /* probe in flash memoryarea */ - u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; - u32 m; - u32 lines = -1; - - wr_dc_cst(IDC_UNALL); - wr_dc_cst(IDC_INVALL); - wr_dc_cst(IDC_DISABLE); - - while (!((m = rd_dc_cst()) & IDC_CERR2)) { - wr_dc_adr(k); - wr_dc_cst(IDC_LDLCK); - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_dc_cst(IDC_UNALL); - wr_dc_cst(IDC_INVALL); - - if (cacheon) - wr_dc_cst(IDC_ENABLE); - else - wr_dc_cst(IDC_DISABLE); - - return lines << 4; -}; - /* ------------------------------------------------------------------------- */ void upmconfig(uint upm, uint *table, uint size) diff --git a/include/common.h b/include/common.h index 48eb223627..423f1023ad 100644 --- a/include/common.h +++ b/include/common.h @@ -195,8 +195,6 @@ void trap_init (ulong); void s_init(void); -int checkicache (void); -int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); void reset_misc (void);