arm: mx6: ddr: cleanup
No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
This commit is contained in:
Nikita Kiryanov
Stefano Babic
parent
c6c2492ad8
commit
3368918f71
@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
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*/
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#define MR(val, ba, cmd, cs1) \
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((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
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const struct mx6_mmdc_calibration *c,
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const struct mx6_ddr3_cfg *m)
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void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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const struct mx6_mmdc_calibration *calib,
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const struct mx6_ddr3_cfg *ddr3_cfg)
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{
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volatile struct mmdc_p_regs *mmdc0;
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volatile struct mmdc_p_regs *mmdc1;
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u32 reg;
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u32 val;
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u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
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u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
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u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
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u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
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u16 CS0_END;
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u16 cs0_end;
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u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
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u8 coladdr;
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int clkper; /* clock period in picoseconds */
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@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
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clock = 400;
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tcwl = 3;
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}
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clkper = (1000*1000)/clock; /* ps */
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clkper = (1000 * 1000) / clock; /* pico seconds */
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todtlon = tcwl;
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taxpd = tcwl;
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tanpd = tcwl;
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tcwl = tcwl;
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switch (m->density) {
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switch (ddr3_cfg->density) {
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case 1: /* 1Gb per chip */
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trfc = DIV_ROUND_UP(110000, clkper) - 1;
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txs = DIV_ROUND_UP(120000, clkper) - 1;
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@ -240,80 +239,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
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break;
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default:
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/* invalid density */
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printf("invalid chip density\n");
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puts("invalid chip density\n");
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hang();
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break;
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}
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txpr = txs;
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switch (m->mem_speed) {
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switch (ddr3_cfg->mem_speed) {
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case 800:
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txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
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if (m->pagesz == 1) {
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txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
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if (ddr3_cfg->pagesz == 1) {
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tfaw = DIV_ROUND_UP(40000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
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} else {
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tfaw = DIV_ROUND_UP(50000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
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}
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break;
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case 1066:
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txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
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if (m->pagesz == 1) {
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txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
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if (ddr3_cfg->pagesz == 1) {
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tfaw = DIV_ROUND_UP(37500, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
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} else {
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tfaw = DIV_ROUND_UP(50000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
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}
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break;
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case 1333:
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txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
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if (m->pagesz == 1) {
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txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
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if (ddr3_cfg->pagesz == 1) {
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tfaw = DIV_ROUND_UP(30000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
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} else {
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tfaw = DIV_ROUND_UP(45000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
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}
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break;
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case 1600:
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txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
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if (m->pagesz == 1) {
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txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
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tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
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if (ddr3_cfg->pagesz == 1) {
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tfaw = DIV_ROUND_UP(30000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
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} else {
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tfaw = DIV_ROUND_UP(40000, clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
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trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
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}
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break;
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default:
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printf("invalid memory speed\n");
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puts("invalid memory speed\n");
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hang();
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break;
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}
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txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
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tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
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tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
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tcksrx = tcksre;
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txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
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tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
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taonpd = DIV_ROUND_UP(2000, clkper) - 1;
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tcksrx = tcksre;
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taofpd = taonpd;
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trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
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twr = DIV_ROUND_UP(15000, clkper) - 1;
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tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
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trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
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tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
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tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
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trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
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twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
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trcd = trp;
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trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
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tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
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twr = DIV_ROUND_UP(15000, clkper) - 1;
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tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
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twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
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trtp = twtr;
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CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
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debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
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cs0_end = (4 * sysinfo->cs_density <= 120) ?
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4 * sysinfo->cs_density + 7 :
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127;
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debug("density:%d Gb (%d Gb per chip)\n",
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sysinfo->cs_density, ddr3_cfg->density);
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debug("clock: %dMHz (%d ps)\n", clock, clkper);
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debug("memspd:%d\n", m->mem_speed);
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debug("memspd:%d\n", ddr3_cfg->mem_speed);
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debug("tcke=%d\n", tcke);
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debug("tcksrx=%d\n", tcksrx);
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debug("tcksre=%d\n", tcksre);
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@ -340,11 +343,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
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debug("twtr=%d\n", twtr);
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debug("trrd=%d\n", trrd);
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debug("txpr=%d\n", txpr);
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debug("CS0_END=%d\n", CS0_END);
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debug("ncs=%d\n", i->ncs);
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debug("Rtt_wr=%d\n", i->rtt_wr);
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debug("Rtt_nom=%d\n", i->rtt_nom);
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debug("SRT=%d\n", m->SRT);
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debug("cs0_end=%d\n", cs0_end);
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debug("ncs=%d\n", sysinfo->ncs);
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debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
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debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
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debug("SRT=%d\n", ddr3_cfg->SRT);
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debug("tcl=%d\n", tcl);
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debug("twr=%d\n", twr);
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@ -354,142 +357,135 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
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* see:
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* appnote, ddr3 spreadsheet
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*/
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mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
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mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
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mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
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mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
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mmdc0->mprddlctl = c->p0_mprddlctl;
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mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
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if (i->dsize > 1) {
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mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
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mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
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mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
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mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
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mmdc1->mprddlctl = c->p1_mprddlctl;
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mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
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mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
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mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
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mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
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mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
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mmdc0->mprddlctl = calib->p0_mprddlctl;
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mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
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if (sysinfo->dsize > 1) {
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mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
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mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
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mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
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mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
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mmdc1->mprddlctl = calib->p1_mprddlctl;
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mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
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}
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/* Read data DQ Byte0-3 delay */
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mmdc0->mprddqby0dl = (u32)0x33333333;
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mmdc0->mprddqby1dl = (u32)0x33333333;
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if (i->dsize > 0) {
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mmdc0->mprddqby2dl = (u32)0x33333333;
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mmdc0->mprddqby3dl = (u32)0x33333333;
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mmdc0->mprddqby0dl = 0x33333333;
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mmdc0->mprddqby1dl = 0x33333333;
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if (sysinfo->dsize > 0) {
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mmdc0->mprddqby2dl = 0x33333333;
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mmdc0->mprddqby3dl = 0x33333333;
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}
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if (i->dsize > 1) {
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mmdc1->mprddqby0dl = (u32)0x33333333;
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mmdc1->mprddqby1dl = (u32)0x33333333;
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mmdc1->mprddqby2dl = (u32)0x33333333;
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mmdc1->mprddqby3dl = (u32)0x33333333;
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if (sysinfo->dsize > 1) {
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mmdc1->mprddqby0dl = 0x33333333;
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mmdc1->mprddqby1dl = 0x33333333;
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mmdc1->mprddqby2dl = 0x33333333;
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mmdc1->mprddqby3dl = 0x33333333;
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}
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/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
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reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
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mmdc0->mpodtctrl = reg;
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if (i->dsize > 1)
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mmdc1->mpodtctrl = reg;
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val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
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mmdc0->mpodtctrl = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpodtctrl = val;
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/* complete calibration */
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reg = (1 << 11); /* Force measurement on delay-lines */
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mmdc0->mpmur0 = reg;
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if (i->dsize > 1)
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mmdc1->mpmur0 = reg;
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val = (1 << 11); /* Force measurement on delay-lines */
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mmdc0->mpmur0 = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpmur0 = val;
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/* Step 1: configuration request */
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mmdc0->mdscr = (u32)(1 << 15); /* config request */
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/* Step 2: Timing configuration */
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reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
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(tfaw << 4) | tcl;
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mmdc0->mdcfg0 = reg;
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reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
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(1 << 15) | /* trpa */
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(twr << 9) | (tmrd << 5) | tcwl;
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mmdc0->mdcfg1 = reg;
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reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
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mmdc0->mdcfg2 = reg;
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reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
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(todtlon << 12) | (todt_idle_off << 4);
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mmdc0->mdotc = reg;
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mmdc0->mdasp = CS0_END; /* CS addressing */
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mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
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(txpdll << 9) | (tfaw << 4) | tcl;
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mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
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(tras << 16) | (1 << 15) /* trpa */ |
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(twr << 9) | (tmrd << 5) | tcwl;
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mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
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mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
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(taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
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mmdc0->mdasp = cs0_end; /* CS addressing */
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/* Step 3: Configure DDR type */
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reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
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(i->mif3_mode << 9) | (i->ralat << 6);
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mmdc0->mdmisc = reg;
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mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
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(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
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(sysinfo->ralat << 6);
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/* Step 4: Configure delay while leaving reset */
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reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
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mmdc0->mdor = reg;
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mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
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(sysinfo->rst_to_cke << 0);
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/* Step 5: Configure DDR physical parameters (density and burst len) */
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coladdr = m->coladdr;
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if (m->coladdr == 8) /* 8-bit COL is 0x3 */
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coladdr = ddr3_cfg->coladdr;
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if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
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coladdr += 4;
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else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
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else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
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coladdr += 1;
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reg = (m->rowaddr - 11) << 24 | /* ROW */
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(coladdr - 9) << 20 | /* COL */
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(1 << 19) | /* Burst Length = 8 for DDR3 */
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(i->dsize << 16); /* DDR data bus size */
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mmdc0->mdctl = reg;
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mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
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(coladdr - 9) << 20 | /* COL */
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(1 << 19) | /* Burst Length = 8 for DDR3 */
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(sysinfo->dsize << 16); /* DDR data bus size */
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/* Step 6: Perform ZQ calibration */
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reg = (u32)0xa1390001; /* one-time HW ZQ calib */
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mmdc0->mpzqhwctrl = reg;
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if (i->dsize > 1)
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mmdc1->mpzqhwctrl = reg;
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val = 0xa1390001; /* one-time HW ZQ calib */
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mmdc0->mpzqhwctrl = val;
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if (sysinfo->dsize > 1)
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mmdc1->mpzqhwctrl = val;
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/* Step 7: Enable MMDC with desired chip select */
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reg = mmdc0->mdctl |
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(1 << 31) | /* SDE_0 for CS0 */
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((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
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mmdc0->mdctl = reg;
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mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
|
||||
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
|
||||
|
||||
/* Step 8: Write Mode Registers to Init DDR3 devices */
|
||||
for (cs = 0; cs < i->ncs; cs++) {
|
||||
for (cs = 0; cs < sysinfo->ncs; cs++) {
|
||||
/* MR2 */
|
||||
reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
|
||||
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
|
||||
((tcwl - 3) & 3) << 3;
|
||||
mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
|
||||
mmdc0->mdscr = MR(val, 2, 3, cs);
|
||||
/* MR3 */
|
||||
mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
|
||||
mmdc0->mdscr = MR(0, 3, 3, cs);
|
||||
/* MR1 */
|
||||
reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
|
||||
((i->rtt_nom & 2) ? 1 : 0) << 6;
|
||||
mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
|
||||
reg = ((tcl - 1) << 4) | /* CAS */
|
||||
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
|
||||
((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
|
||||
mmdc0->mdscr = MR(val, 1, 3, cs);
|
||||
/* MR0 */
|
||||
val = ((tcl - 1) << 4) | /* CAS */
|
||||
(1 << 8) | /* DLL Reset */
|
||||
((twr - 3) << 9); /* Write Recovery */
|
||||
/* MR0 */
|
||||
mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
|
||||
mmdc0->mdscr = MR(val, 0, 3, cs);
|
||||
/* ZQ calibration */
|
||||
reg = (1 << 10);
|
||||
mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
|
||||
val = (1 << 10);
|
||||
mmdc0->mdscr = MR(val, 0, 4, cs);
|
||||
}
|
||||
|
||||
/* Step 10: Power down control and self-refresh */
|
||||
reg = (tcke & 0x7) << 16 |
|
||||
5 << 12 | /* PWDT_1: 256 cycles */
|
||||
5 << 8 | /* PWDT_0: 256 cycles */
|
||||
1 << 6 | /* BOTH_CS_PD */
|
||||
(tcksrx & 0x7) << 3 |
|
||||
(tcksre & 0x7);
|
||||
mmdc0->mdpdc = reg;
|
||||
mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
|
||||
mmdc0->mdpdc = (tcke & 0x7) << 16 |
|
||||
5 << 12 | /* PWDT_1: 256 cycles */
|
||||
5 << 8 | /* PWDT_0: 256 cycles */
|
||||
1 << 6 | /* BOTH_CS_PD */
|
||||
(tcksrx & 0x7) << 3 |
|
||||
(tcksre & 0x7);
|
||||
mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
|
||||
|
||||
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
|
||||
mmdc0->mpzqhwctrl = (u32)0xa1390003;
|
||||
if (i->dsize > 1)
|
||||
mmdc1->mpzqhwctrl = (u32)0xa1390003;
|
||||
val = 0xa1390003;
|
||||
mmdc0->mpzqhwctrl = val;
|
||||
if (sysinfo->dsize > 1)
|
||||
mmdc1->mpzqhwctrl = val;
|
||||
|
||||
/* Step 12: Configure and activate periodic refresh */
|
||||
reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
|
||||
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */
|
||||
mmdc0->mdref = reg;
|
||||
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
|
||||
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */
|
||||
|
||||
/* Step 13: Deassert config request - init complete */
|
||||
mmdc0->mdscr = (u32)0x00000000;
|
||||
mmdc0->mdscr = 0x00000000;
|
||||
|
||||
/* wait for auto-ZQ calibration to complete */
|
||||
mdelay(1);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user