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Merge git://git.denx.de/u-boot-x86

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This commit is contained in:
Tom Rini 2018-08-20 13:41:37 -04:00
commit 3313e90844
22 changed files with 144 additions and 174 deletions
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4
Makefile
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@ -375,6 +375,10 @@ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
KBUILD_CFLAGS += -fshort-wchar
KBUILD_AFLAGS := -D__ASSEMBLY__
# Don't generate position independent code
KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
KBUILD_AFLAGS += $(call cc-option,-fno-PIE)
# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)

20
arch/x86/cpu/coreboot/Kconfig
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@ -3,26 +3,26 @@ if TARGET_COREBOOT
config SYS_COREBOOT
bool
default y
imply SYS_NS16550
imply SCSI
imply SCSI_AHCI
imply AHCI_PCI
imply E1000
imply ICH_SPI
imply MMC
imply MMC_PCI
imply MMC_SDHCI
imply MMC_SDHCI_SDMA
imply SCSI
imply SCSI_AHCI
imply SPI_FLASH
imply SYS_NS16550
imply USB
imply USB_EHCI_HCD
imply USB_XHCI_HCD
imply USB_STORAGE
imply USB_KEYBOARD
imply VIDEO_COREBOOT
imply E1000
imply ETH_DESIGNWARE
imply PCH_GBE
imply RTL8169
imply CMD_CBFS
imply FS_CBFS
config CBMEM_CONSOLE
bool
default y
imply CBMEM_CONSOLE
endif

9
arch/x86/cpu/coreboot/coreboot.c
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@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <usb.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
@ -75,12 +76,10 @@ int last_stage_init(void)
if (gd->flags & GD_FLG_COLD_BOOT)
timestamp_add_to_bootstage();
/* start usb so that usb keyboard can be used as input device */
usb_init();
board_final_cleanup();
return 0;
}
int misc_init_r(void)
{
return 0;
}

2
arch/x86/dts/Makefile
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@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
conga-qeval20-qa3-e3845.dtb \
coreboot.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
dfi-bt700-q7x-151.dtb \
@ -17,7 +18,6 @@ dtb-y += bayleybay.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
broadwell_som-6896.dtb \
baytrail_som-db5800-som-6867.dtb
targets += $(dtb-y)

1
arch/x86/dts/bayleybay.dts
View File

@ -15,7 +15,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Bayley Bay";

52
arch/x86/dts/broadwell_som-6896.dts
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@ -1,52 +0,0 @@
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Advantech SOM-6896";
compatible = "advantech,som-6896", "intel,broadwell";
aliases {
spi0 = &spi;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
pci {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q128", "spi-flash";
memory-map = <0xff000000 0x01000000>;
};
};
};
};
};

1
arch/x86/dts/chromebook_link.dts
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@ -8,7 +8,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";

1
arch/x86/dts/chromebook_samus.dts
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@ -8,7 +8,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Samus";

1
arch/x86/dts/chromebox_panther.dts
View File

@ -5,7 +5,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Panther";

45
arch/x86/dts/coreboot.dts Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*
* Generic coreboot payload device tree for x86 targets
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
compatible = "coreboot,x86-payload";
aliases {
serial0 = &serial;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
};
coreboot-fb {
compatible = "coreboot-fb";
};
};

5
arch/x86/dts/coreboot_fb.dtsi
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@ -1,5 +0,0 @@
/ {
coreboot-fb {
compatible = "coreboot-fb";
};
};

4
arch/x86/dts/efi-x86_payload.dts
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@ -30,6 +30,10 @@
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;

1
arch/x86/dts/minnowmax.dts
View File

@ -14,7 +14,6 @@
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Minnowboard Max";

28
board/coreboot/coreboot/Kconfig
View File

@ -9,35 +9,15 @@ config SYS_VENDOR
config SYS_SOC
default "coreboot"
config SYS_CONFIG_NAME
default "coreboot"
config SYS_TEXT_BASE
default 0x01110000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
imply SPI_FLASH_ATMEL
imply SPI_FLASH_EON
imply SPI_FLASH_GIGADEVICE
imply SPI_FLASH_MACRONIX
imply SPI_FLASH_SPANSION
imply SPI_FLASH_STMICRO
imply SPI_FLASH_SST
imply SPI_FLASH_WINBOND
comment "coreboot-specific options"
config SYS_CONFIG_NAME
string "Board configuration file"
default "qemu-x86"
help
This option selects the board configuration file in include/configs/
directory to be used to build U-Boot for coreboot.
config DEFAULT_DEVICE_TREE
string "Board Device Tree Source (dts) file"
default "qemu-x86_i440fx"
help
This option selects the board Device Tree Source (dts) file in
arch/x86/dts/ directory to be used to build U-Boot for coreboot.
select BOARD_EARLY_INIT_R
config SYS_CAR_ADDR
hex "Board specific Cache-As-RAM (CAR) address"

2
board/coreboot/coreboot/Makefile
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@ -10,4 +10,4 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
obj-y += coreboot_start.o
obj-y += start.o coreboot.o

17
board/coreboot/coreboot/coreboot.c Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
int board_early_init_r(void)
{
/*
* Make sure PCI bus is enumerated so that peripherals on the PCI bus
* can be discovered by their drivers
*/
pci_init();
return 0;
}

0
board/coreboot/coreboot/coreboot_start.S → board/coreboot/coreboot/start.S
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18
configs/coreboot_defconfig
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@ -4,28 +4,25 @@ CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@ -34,11 +31,8 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="coreboot"
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
# CONFIG_PCI_PNP is not set
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_TPM=y

22
doc/README.x86
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@ -47,21 +47,6 @@ on other architectures, like below:
$ make coreboot_defconfig
$ make all
Note this default configuration will build a U-Boot payload for the QEMU board.
To build a coreboot payload against another board, you can change the build
configuration during the 'make menuconfig' process.
x86 architecture --->
...
(qemu-x86) Board configuration file
(qemu-x86_i440fx) Board Device Tree Source (dts) file
(0x01920000) Board specific Cache-As-RAM (CAR) address
(0x4000) Board specific Cache-As-RAM (CAR) size
Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
to point to a new board. You can also change the Cache-As-RAM (CAR) related
settings here if the default values do not fit your new board.
Build Instructions for U-Boot as main bootloader
------------------------------------------------
@ -427,17 +412,10 @@ To enable video you must enable these options in coreboot:
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- Keep VESA framebuffer
And include coreboot_fb.dtsi in your board's device tree source file, like:
/include/ "coreboot_fb.dtsi"
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
at this point. Patches are welcome if you figure out anything wrong.
Test with QEMU for bare mode
----------------------------
QEMU is a fancy emulator that can enable us to test U-Boot without access to

25
drivers/timer/tsc_timer.c
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@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count)
return 0;
}
static void tsc_timer_ensure_setup(void)
static void tsc_timer_ensure_setup(bool stop)
{
if (gd->arch.tsc_base)
return;
gd->arch.tsc_base = rdtsc();
/*
* If there is no clock frequency specified in the device tree,
* calibrate it by ourselves.
*/
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void)
if (fast_calibrate)
goto done;
if (stop)
panic("TSC frequency is ZERO");
else
return;
done:
gd->arch.clock_rate = fast_calibrate * 1000000;
@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (!uc_priv->clock_rate) {
tsc_timer_ensure_setup();
uc_priv->clock_rate = gd->arch.clock_rate;
/* Try hardware calibration first */
tsc_timer_ensure_setup(false);
if (!gd->arch.clock_rate) {
/*
* Use the clock frequency specified in the
* device tree as last resort
*/
if (!uc_priv->clock_rate)
panic("TSC frequency is ZERO");
} else {
gd->arch.tsc_base = rdtsc();
uc_priv->clock_rate = gd->arch.clock_rate;
}
return 0;
@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void)
* clock rate can only be calibrated via some hardware ways. Specifying
* it in the device tree won't work for the early timer.
*/
tsc_timer_ensure_setup();
tsc_timer_ensure_setup(true);
return gd->arch.clock_rate;
}

32
include/configs/coreboot.h Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
/* ATA/IDE support */
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 4
#define CONFIG_SYS_ATA_BASE_ADDR 0
#define CONFIG_SYS_ATA_DATA_OFFSET 0
#define CONFIG_SYS_ATA_REG_OFFSET 0
#define CONFIG_SYS_ATA_ALT_OFFSET 0
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
#endif /* __CONFIG_H */

26
include/configs/som-6896.h
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@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the SOM-6896
*
* Copyright (C) 2015 NovaTech LLC
* George McCollister <george.mccollister@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x00ff0000
#endif /* __CONFIG_H */