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Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-09-03 14:59:18 +02:00
commit 31043e20ae
5 changed files with 10 additions and 5 deletions
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3
include/configs/dalmore.h
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@ -21,9 +21,6 @@
#include "tegra114-common.h"
/* Must be off for Dalmore to boot !?!? FIXME */
#define CONFIG_SYS_DCACHE_OFF
/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
#define CONFIG_OF_CONTROL

3
include/configs/tegra-common.h
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@ -17,8 +17,6 @@
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_SYS_CACHELINE_SIZE 32
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
@ -135,6 +133,7 @@
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
/* Defines for SPL */
#define CONFIG_SPL

3
include/configs/tegra114-common.h
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@ -18,6 +18,9 @@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/

3
include/configs/tegra20-common.h
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@ -9,6 +9,9 @@
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
/* Cortex-A9 uses a cache line size of 32 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Errata configuration
*/

3
include/configs/tegra30-common.h
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@ -9,6 +9,9 @@
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
/* Cortex-A9 uses a cache line size of 32 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Errata configuration
*/