armv8: lx2160a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -24,6 +24,7 @@ endif
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ifneq ($(CONFIG_ARCH_LX2160A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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obj-y += icid.o lx2160_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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48
arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
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48
arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
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@ -0,0 +1,48 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <asm/arch-fsl-layerscape/fsl_portals.h>
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struct icid_id_table icid_tbl[] = {
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SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
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SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
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SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
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SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
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SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
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SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
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SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
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SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
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#ifdef CONFIG_FSL_CAAM
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SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
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#endif
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};
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int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
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@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)
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#endif
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#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
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defined(CONFIG_ARCH_LS2080A)
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defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
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set_icids();
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#endif
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}
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@ -447,7 +447,9 @@ struct ccsr_gur {
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u8 res_538[0x550 - 0x538]; /* add more registers when needed */
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u32 sata1_amqr;
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u32 sata2_amqr;
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u8 res_558[0x570-0x558]; /* add more registers when needed */
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u32 sata3_amqr;
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u32 sata4_amqr;
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u8 res_560[0x570 - 0x560]; /* add more registers when needed */
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u32 misc1_amqr;
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u8 res_574[0x590-0x574]; /* add more registers when needed */
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u32 spare1_amqr;
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@ -108,5 +108,7 @@
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#define FSL_EDMA_STREAM_ID 70
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#define FSL_GPU_STREAM_ID 71
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#define FSL_DISPLAY_STREAM_ID 72
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#define FSL_SATA3_STREAM_ID 73
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#define FSL_SATA4_STREAM_ID 74
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#endif
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@ -27,6 +27,7 @@
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#include "../common/qixis.h"
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#include "../common/vid.h"
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#include <fsl_immap.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#ifdef CONFIG_EMC2305
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#include "../common/emc2305.h"
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@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd)
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fdt_fsl_mc_fixup_iommu_map_entry(blob);
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fdt_fixup_board_enet(blob);
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#endif
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fdt_fixup_icid(blob);
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return 0;
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}
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@ -93,8 +93,7 @@ typedef struct ccsr_sec {
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struct {
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u32 ms; /* DECO LIODN Register, MS */
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u32 ls; /* DECO LIODN Register, LS */
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} decoliodnr[8];
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u8 res4[0x40];
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} decoliodnr[16];
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u32 dar; /* DECO Avail Register */
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u32 drr; /* DECO Reset Register */
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u8 res5[0x4d8];
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